Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids

• US 10,607,989 B2
• Filed: 07/02/2018
• Issued: 03/31/2020
• Est. Priority Date: 12/18/2014
• Status: Active Grant

• Current Assignee: Cardea Bio, Inc.
• Original Assignee: Nanomedical Diagnostics, Inc. (Cardea Bio, Inc.)
• Inventors: Hoffman, Paul
• Primary Examiner(s): Bachner, Robert G
• Application Number:
  US16/025,794
• Publication Number:
  US 20180315750A1
• Time in Patent Office: 638 Days
• CPC Class Codes: C12Q 1/6874 involving nucleic acid arrays, e.g. sequencing by hybridisation
• CPC Class Codes: C12Q 2565/607 being a sensor, e.g. electrode
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4146 involving nanosized elements, e.g. nanotubes, nanowires
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/66045 Field-effect transistors

Abstract

Provided herein are integrated circuits for use in performing analyte measurements and methods of fabricating the same. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. The methods for fabricating the integrated circuits include steps of depositing an insulating layer on a semiconducting substrate, and forming trenches in the insulating dielectric layer. Conductive material may be deposited in the trenches to form electrodes, and the insulating layer may be conditioned so that the electrodes protrude above the insulating layer. A 2D material, such as graphene, may be deposited on to electrodes to form a channel between the electrodes.

Claims

1. A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising:

providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being defined by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces;

depositing a first insulating dielectric layer onto a top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member;

forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region;

depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements;

conditioning the first insulating dielectric layer in a manner so that a side and top surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer; and

depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes.

2. The method according to claim 1, wherein the 2D material comprises a material selected from the group consisting of:

Graphene;

Molybdenum disulfide (MoS₂);

Phosphorene (black phosphorous);

Silicene, Borophene, Tungsten disulfide (WS₂);

Boron Nitride;

WSe₂;

Stanene (2D tin);

Graphane;

Germanane;

Nickel HITP; and

Mxenes (Ti2C, [Ti0.5,Nb0.5], V2C, Nb2C, Ti3C2, Ti3CN, Nb4C3, Ta4C3).

3. The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer is accomplished by etching.

4. The method according to claim 3, wherein the step of etching the first insulating dielectric layer is accomplished by one or more of dry etching and wet etching.

5. The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer further comprises depositing a second layer of conductive material on each of the plurality of electrodes so that each of the plurality of electrodes extends further above the surface of the insulating dielectric layer.

6. The method according to claim 1, further comprising forming an opening in the 2D material layer proximate each electrode so as to expose the top surface of each electrode.

7. The method according to claim 6 wherein the forming of the opening in the 2D material layer proximate each electrode is accomplished using a photoresist and etching process.

8. The method according to claim 7, further comprising depositing a second layer of conductive material over each opening of the 2D material layer so that the second layer of conductive material contacts the first conductive material, fills the opening, and further extends above the 2D material layer so as to contact a side and top surface of the 2D material layer.

9. The method according to claim 1, further comprising patterning the 2D material layer.

10. The method according to claim 9, further comprising depositing a second insulating material layer over the patterned 2D material layer and patterning the second insulating material to form a well having a bottom surface proximate the channel region.

11. A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising:

providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being surrounded by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces;

providing a first insulating dielectric layer on top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member;

forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region;

depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements;

depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes;

forming an opening in the 2D material proximate each electrode so as to expose at least the top surface of each electrode; and

depositing a second layer of conductive material over each opening of the 2D material layer so that the second layer of conductive material contacts at least the top surface of the electrode, fills the opening, and further extends above the 2D material layer so as to contact a side and top surface of the 2D material layer.

12. The method according to claim 11, further comprising conditioning the first insulating dielectric layer in a manner so that a surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer.

13. The method according to claim 12, further comprising patterning the 2D material layer.

14. The method according to claim 13, further comprising depositing a second insulating material layer over the 2D material layer and patterning the second insulating material to form a well having a bottom surface proximate the channel region.

15. The method according to claim 14, wherein the 2D material comprises a material selected from the group consisting of:

graphene;

Molybdenum disulfide (MoS₂);

Phosphorene (black phosphorous);

Silicene, Borophene, Tungsten disulfide (WS₂);

Boron Nitride;

WSe₂;

Stanene (2D tin);

Graphane;

Germanane;

Nickel HITP; and

Mxenes (Ti2C, [Ti0.5,Nb0.5], V2C, Nb2C, Ti3C2, Ti3CN, Nb4C3, Ta4C3).

16. A method for securing an electrode to a 2D material layer, the method comprising:

providing a semi-conducting substrate, the substrate having a planar surface;

providing a first insulating dielectric layer onto the top planar surface of the substrate, the first insulating dielectric layer having a top surface;

preparing a plurality of electrodes within the first insulating dielectric layer, each of the plurality of electrodes having a dimension even with or projecting above the top surface of the first insulating dielectric surface;

depositing a 2D material layer on the plurality of electrodes to form a contact between the electrodes and the 2D material layer; and

patterning the 2D material layer to form at least one channel contacting an electrode on each of the ends of the channel.

17. The method according to claim 16, wherein the plurality of electrodes comprise a first electrode serving as a source electrode, and a second electrode serving as a drain electrode.

18. The method according to claim 17, wherein the semi-conducting substrate comprises one or more transistor elements, the one or more transistor elements being in contact with the source and drain electrodes.

19. The method according to claim 17, wherein the 2D material is composed of one of graphene, Molybdenum disulfide (MoS₂), Phosphorene (black phosphorous), Silicene, Borophene, Tungsten disulfide (WS₂), Boron Nitride, WSe₂, Stanene (2D tin), Graphane, Germanane, Nickel HITP, or Mxenes (Ti2C, (Ti0.5,Nb0.5), V2C, Nb2C, Ti3C2, Ti3CN, Nb4C3, Ta4C3).

20. The method according to claim 17, wherein the 2D material is composed of graphene.