3-dimensional nor strings with segmented shared source regions

• US 10,608,008 B2
• Filed: 06/12/2018
• Issued: 03/31/2020
• Est. Priority Date: 06/20/2017
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli, Cernea, Raul Adrian
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US16/006,612
• Publication Number:
  US 20180366485A1
• Time in Patent Office: 658 Days
• Field of Search: None
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

Claims

1. A NOR string, comprising;

a bit line;

first and second source lines that are electrically isolated from each other;

individually addressable first, second, third and fourth thin-film storage transistors sharing the bit line, wherein the first and second thin-film storage transistors share the first source line.

2. The NOR string of claim 1, wherein the first, second, third and fourth thin-film storage transistors of the NOR string are formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, the active strip comprising first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the bit line is formed in the first semiconductor sublayer, and wherein the first and second source lines are formed in the second semiconductor sublayer.

3. The NOR string of claim 2, further comprising a conductive layer provided adjacent the first semiconductor sublayer, the conductive sublayer providing a low-resistivity path in the bit line.

4. The NOR string of claim 3, wherein the bit line is selectively electrically connected to circuitry formed in the semiconductor substrate.

5. The NOR string of claim 2, wherein the NOR string is one of a plurality of like NOR strings formed one on top of another in a stack of active strips.

6. The NOR string of claim 5, wherein the stack of active strips is one of a plurality of like stacks of active strips separated from each other by trenches running lengthwise along a first direction.

7. The NOR string of claim 6, wherein the first and second source lines of each NOR string are separated from each other by an insulation material provided in a trench running along a second direction substantially orthogonal to the first direction.

8. The NOR string of claim 1 further comprising first and second pre-charge transistors that are provided to connect the first and second source lines, respectively, with the bit line.

9. The NOR string of claim 8 wherein, during a read or programming operation on the first or second thin-film storage transistor in the NOR string, the second source line of the NOR string and the bit line are held at substantially the same voltage.