Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts

• US 10,608,092 B2
• Filed: 12/16/2017
• Issued: 03/31/2020
• Est. Priority Date: 06/01/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Yilmaz, Hamza, Chen, John, Ng, Daniel, Li, Wenjun
• Primary Examiner(s): Mulpuri, Savitr
• Application Number:
  US15/844,520
• Publication Number:
  US 20180269293A1
• Time in Patent Office: 836 Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 29/8725 : of the trench MOS barrier type [TMBS]

Abstract

This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

Claims

1. A method of forming a shield gate trench (SGT) MOSFET with source body shorting silicide comprising:

forming trenches by applying a first photo mask with semiconductor protuberances in between;

forming a bottom dielectric layer in a bottom of the trench;

forming a shield electrode at the bottom of the trench on top of the bottom dielectric layer and forming a dielectric layer surrounding the shield electrode;

forming an inter-electrode-dielectric over the shield electrode;

forming an upper gate dielectric layer on an upper trench sidewalls;

forming a recessed gate electrode on top of the inter-electrode-dielectric layer surrounded by the upper gate dielectric layer;

forming source regions along the top surface of semiconductor protuberance sidewalls, using the recessed gate electrode as a mask;

forming a body region between and below source regions; and

forming a source/body silicide substantially across the entire top surface of the semiconductor protuberance;

forming contacts with a second photomask for contacting the source and body regions, and forming a source metal and a gate metal with a third photomask; and

wherein the steps of forming the source and body regions further comprising a step of applying an additional mask to protect a Schottky diode region.

2. The method of claim 1 further comprising a step of removing the top portion of the semiconductor protuberance to allow the source/body silicide to contact the body region between the source regions.

5. The method of claim 1 further comprising a step of applying two additional masks for forming an ESD structure of back-to-back gate-source diodes.

3. A method of forming a shield gate trench (SGT) MOSFET with source body shorting silicide comprising:

forming trenches by applying a first photo mask with semiconductor protuberances in between;

forming a bottom dielectric layer in a bottom of the trench;

forming a shield electrode at the bottom of the trench on top of the bottom dielectric layer and forming a dielectric layer surrounding the shield electrode;

forming an inter-electrode-dielectric over the shield electrode;

forming an upper gate dielectric layer on an upper trench sidewalls;

forming a recessed gate electrode on top of the inter-electrode-dielectric layer surrounded by the upper gate dielectric layer;

forming source regions along the top surface of semiconductor protuberance sidewalls, using the recessed gate electrode as a mask;

forming a body region between and below source regions;

forming a source/body silicide substantially across the entire top surface of the semiconductor protuberance;

forming contacts with a second photomask for contacting the source and body regions, and forming a source metal and a gate metal with a third photomask; and

using two additional masks for forming an ESD structure of back-to-back gate-source diodes.

4. The method of claim 3 further comprising a step of using an additional mask to protect a Schottky diode region while forming the source and body regions.