Power semiconductor devices

• US 10,608,106 B2
• Filed: 04/18/2018
• Issued: 03/31/2020
• Est. Priority Date: 01/30/2018
• Status: Active Grant

• Current Assignee: University of Electronic Science and Technology of China
• Original Assignee: University of Electronic Science and Technology of China
• Inventors: Qiao, Ming, Wang, Zhengkang, Wang, Ruidi, Qi, Zhao, Zhang, Bo
• Primary Examiner(s): Green, Telly D
• Application Number:
  US15/955,706
• Publication Number:
  US 20190237576A1
• Time in Patent Office: 713 Days
• Field of Search: None
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0852 of DMOS transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.

Claims

1. A power semiconductor device, comprising:

a first conductivity type semiconductor substrate,

a drain metal electrode connected to a bottom of the first conductivity type semiconductor substrate and located at a bottom of the power semiconductor device,

a first conductivity type semiconductor drift region disposed on an upper surface of the first conductivity type semiconductor substrate,

a second conductivity type semiconductor body region disposed on an upper surface of the first conductivity type semiconductor drift region, and

a first conductivity type semiconductor source region and an anti-punch-through structure disposed inside the second conductivity type semiconductor body region;

wherein

the anti-punch-through structure is a second conductivity type semiconductor body contact region;

a source metal electrode disposed on a surface of the power semiconductor device connects the first conductivity type semiconductor source region and the anti-punch-through structure,

a lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or a distance between the lower surface of anti-punch-through structure and the upper surface of the first conductivity type semiconductor drift region is less than 0.5 μ

m to prevent punch-through breakdown,

a dielectric layer extends through the second conductivity type semiconductor body region and into the first conductive type semiconductor drift region,

a control gate electrode is disposed in the dielectric layer,

a gate dielectric is formed by the dielectric layer between the control gate electrode and the second conductivity type semiconductor body region and the first conductivity type semiconductor drift region, and

a distance between the anti-punch-through structure and the gate dielectric is less than 0.3 μ

m; and

a thickness of the gate dielectric between the control gate electrode and the second conductivity type semiconductor body region and the first conductivity type semiconductor drift region is greater than 0.05 μ

M.

2. The power semiconductor device according to claim 1, wherein a doping concentration of the second conductivity type semiconductor body region is less than 10¹⁵ cm⁻

3.

3. The power semiconductor device according to claim 1, wherein a part of the second conductivity type semiconductor body region between the first conductivity type semiconductor source region and the first conductivity type semiconductor drift region and below the gate dielectric forms a conduction channel region when the power semiconductor device is turned on, and a length of the conduction channel region is less than 0.5 μ

m.

4. The power semiconductor device according to claim 1, wherein an upper surface of the control gate electrode is not higher than a lower surface of the first conductivity type semiconductor source region;

and/or a lower surface of the control gate electrode is not lower than the upper surface of the first conductivity type semiconductor drift region.

5. The power semiconductor device according to claim 1, wherein when the anti-punch-through structure is a metal structure, a short-circuited region is disposed inside the second conductivity type semiconductor body region, and the short-circuited region is in contact with the first conductivity type semiconductor source region and the metal structure.

6. The power semiconductor device according to claim 1, wherein a second source electrode is disposed below the control gate electrode of the dielectric layer.

7. The power semiconductor device according to claim 6, wherein a lower surface of the control gate electrode is higher than the upper surface of the first conductivity type semiconductor drift region.

8. The power semiconductor device according to claim 2, wherein a second source electrode is disposed below the control gate electrode of the dielectric layer.

9. The power semiconductor device according to claim 6, wherein the control gate electrode is divided into a first electrode and a second electrode;

an upper surface of the second source electrode is in contact with the source metal electrode.

10. The power semiconductor device according to claim 6, wherein an alternately distributed second conductivity type strip region and a first conductivity type strip region are provided in the first conductivity type semiconductor drift region.