Logic drive using standard commodity programmable logic IC chips

• US 10,608,638 B2
• Filed: 05/22/2019
• Issued: 03/31/2020
• Est. Priority Date: 05/24/2018
• Status: Active Grant

• Current Assignee: Icometrue Company Ltd.
• Original Assignee: Icometrue Company Ltd.
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung
• Primary Examiner(s): Crawford, Jason
• Application Number:
  US16/420,077
• Publication Number:
  US 20190363715A1
• Time in Patent Office: 314 Days
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/1776 for memories

Abstract

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

Claims

1. A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising:

a programmable logic circuit configured to be programmed to perform a logic operation, comprising a plurality of input points for a first input data set for the logic operation, a plurality of first memory cells configured to store a plurality of resulting values of a look-up table (LUT), a multiplexer configured to select, in accordance with the first input data set, a resulting value from the plurality of resulting values of the look-up table (LUT) as an output data for the logic operation, and an output point for the output data for the logic operation;

a plurality of I/O ports; and

at least one I/O-port selection pad configured to select a first port from the plurality of I/O ports in a first clock cycle to pass a first information associated with the first input data set to the plurality of input points of the programmable logic circuit.

2. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1, wherein the at least one I/O-port selection pad comprises at least one input selection pad configured to activate at least one receiver of the first port in the first clock cycle to receive the first information associated with the first input data set to the plurality of input points of the programmable logic circuit.

3. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 2, wherein the at least one receiver is provided by an I/O circuit of the first port having an input capacitance greater than 2 pF.

4. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 2, wherein the first port comprises at least one I/O pad coupling to the at least one receiver to pass the first information associated with the first input data set to the at least one receiver.

5. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 4, wherein the at least one I/O pad has the number greater than or equal to 4, and the at least one receiver has the number greater than or equal to 4.

6. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1, wherein the at least one I/O-port selection pad comprises at least one output selection pad configured to disable at least one driver of the first port in the first clock cycle.

7. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1, wherein the at least one I/O-port selection pad is configured to select a second port from the plurality of I/O ports in the first clock cycle to pass a second information associated with the output data from the output point of the programmable logic circuit.

8. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 7, wherein the at least one I/O-port selection pad comprises at least one output selection pad configured to enable at least one driver of the second port in the first clock cycle to drive the second information associated with the output data from the output point of the programmable logic circuit.

9. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 8, wherein the at least one driver is provided by an I/O circuit of the second port having an input capacitance greater than 2 pF.

10. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 8, wherein the second port comprises at least one I/O pad coupling to the at least one driver to pass the second information associated with the output data from the at least one driver.

11. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 10, wherein the at least one I/O pad has the number greater than or equal to 4, and the at least one driver has the number greater than or equal to 4.

12. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 7, wherein the at least one I/O-port selection pad comprises at least one input selection pad configured to inhibit at least one receiver of the second port in the first clock cycle.

13. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1 further comprising a chip-enable pad configured to enable the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

14. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1, wherein the at least one I/O-port selection pad is configured to select the first port from the plurality of I/O ports in a second clock cycle to pass second information associated with the output data from the output point of the programmable logic circuit.

15. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 14, wherein the at least one I/O-port selection pad comprises at least one output selection pad configured to enable at least one driver of the first port in the second clock cycle to drive the second information associated with the output data from the output point of the programmable logic circuit.

16. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 15, wherein the first port comprises at least one I/O pad coupling to the at least one driver to pass the second information associated with the output data from the at least one driver.

17. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 16, wherein the at least one I/O pad has the number greater than or equal to 4, and the at least one driver has the number greater than or equal to 4.

18. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1 further comprising a plurality of switches and a plurality of second memory cells configured to store a plurality of programming codes configured to control the plurality of switches, wherein in the first clock the first port is configured to pass the first information associated with the first input data set to the plurality of input points of the programmable logic circuit through the plurality of switches.

19. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1, wherein the multiplexer has a first set of input points for the first input data set for the logic operation and a second set of input points for a second input data set associated with the plurality of resulting values of the look-up table (LUT), wherein the multiplexer is configured to select, in accordance with the first input data set, the resulting value from the plurality of resulting values of the look-up table (LUT) associated with the second input data set as the output data for the logic operation.

20. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1, wherein each of the plurality of first memory cells comprises a static random-access memory (SRAM) cell.

21. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 1, wherein the programmable logic circuit is configured to be programmed to perform the logic operation for multiplication.

22. A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising:

a programmable logic circuit configured to be programmed to perform a logic operation, comprising a plurality of input points for a first input data set for the logic operation, a plurality of first memory cells configured to store a plurality of resulting values of a look-up table (LUT), a multiplexer configured to select, in accordance with the first input data set, a resulting value from the plurality of resulting values of the look-up table (LUT) as an output data for the logic operation, and an output point for the output data for the logic operation;

a plurality of I/O ports; and

at least one I/O-port selection pad configured to select a port from the plurality of I/O ports to pass information associated with the output data from the output point of the programmable logic circuit.

23. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 22, wherein the at least one I/O-port selection pad comprises at least one output selection pad configured to enable at least one driver of the port to drive the information associated with the output data from the output point of the programmable logic circuit.

24. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 23, wherein the at least one driver is provided by an I/O circuit of the port having an input capacitance greater than 2 pF.

25. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 23, wherein the port comprises at least one I/O pad coupling to the at least one driver to pass the information associated with the output data from the at least one driver.

26. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 25, wherein the at least one I/O pad has the number greater than or equal to 4, and the at least one driver has the number greater than or equal to 4.

27. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 22, wherein the at least one I/O-port selection pad comprises at least one input selection pad configured to inhibit at least one receiver of the port.

28. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 22 further comprising a switch and a plurality of second memory cells configured to store a plurality of programming codes configured to control the switch, wherein the port is configured to pass the second information associated with the output data from the output point of the programmable logic circuit through the switch.

29. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 22, wherein the multiplexer has a first set of input points for the first input data set for the logic operation and a second set of input points for a second input data set associated with the plurality of resulting values of the look-up table (LUT), wherein the multiplexer is configured to select, in accordance with the first input data set, the resulting value from the plurality of resulting values of the look-up table (LUT) associated with the second input data set as the output data for the logic operation.

30. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 22, wherein each of the plurality of first memory cells comprises a static random-access memory (SRAM) cell.

31. The field-programmable-gate-array (FPGA) integrated-circuit (IC) chip of claim 22, wherein the programmable logic circuit is configured to be programmed to perform the logic operation for multiplication.