Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells

• US 10,608,642 B2
• Filed: 01/21/2019
• Issued: 03/31/2020
• Est. Priority Date: 02/01/2018
• Status: Active Grant

• Current Assignee: Icometrue Company Ltd.
• Original Assignee: Icometrue Company Ltd.
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US16/253,206
• Publication Number:
  US 20190245543A1
• Time in Patent Office: 435 Days
• Field of Search: None
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/92225 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/1737 : using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 : Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 : for memories
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 19/21 : EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element
• CPC Class Codes: H10B 10/15 : comprising a resistor load element
• CPC Class Codes: H10B 61/00 : Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/10 : comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/20 : comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 : of the metal-insulator-metal type
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Claims

1. A semiconductor integrated-circuit (IC) chip configured to be programmed to perform a logic operation, comprising:

a semiconductor substrate;

a first layer at a surface of the semiconductor substrate, wherein the first layer comprises a plurality of transistors at the surface of the semiconductor substrate;

a second layer over the first layer and the semiconductor substrate, wherein the second layer comprises a plurality of non-volatile memory cells over the first layer, wherein the plurality of non-volatile memory cells comprises a first memory cell configured to store a resulting value for a look-up table (LUT); and

a sense amplifier configured to sense an input data at a first input point of the sense amplifier by comparing the input data of the sense amplifier with a voltage at a second input point of the sense amplifier to generate an output data at an output point of the sense amplifier, wherein the input data of the sense amplifier is associated with the resulting value stored in the first memory cell, wherein the plurality of transistors comprise a plurality of first transistors provided for a plurality of static-random-access-memory (SRAM) cells of the look-up table (LUT) and a plurality of second transistors provided for a multiplexer, wherein the plurality of static-random-access-memory (SRAM) cells of the look-up table (LUT) comprises a second memory cell configured to store data associated with the output data at the output point of the sense amplifier, wherein the multiplexer comprises a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set associated with the look-up table (LUT), wherein the second input data set comprises data associated with the data stored in the second memory cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation.

2. The semiconductor integrated-circuit (IC) chip of claim 1, wherein the first memory cell comprises a resistive-random-access-memory (RRAM) cell configured to store the resulting value.

3. The semiconductor integrated-circuit (IC) chip of claim 1, wherein the first memory cell comprises a magnetoresistive-random-access-memory (MRAM) cell configured to store the resulting value.

4. The semiconductor integrated-circuit (IC) chip of claim 1 comprising a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

5. The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a transistor configured to control connection between the first memory cell and the first input point of the sense amplifier based on a voltage level at a gate terminal of the transistor.

6. The semiconductor integrated-circuit (IC) chip of claim 1, wherein the first memory cell comprises a self-select (SS) resistive random access memory (RRAM) cell configured to pass electric current therethrough based on a bias between two ends thereof, wherein one of the two ends of the self-select (SS) resistive random access memory (RRAM) cell couples to the first input point of the sense amplifier.

7. The semiconductor integrated-circuit (IC) chip of claim 6, wherein the self-select (SS) resistive random access memory (RRAM) cell comprises first and second electrodes, an oxide layer between the first and second electrodes and an insulating layer between the oxide layer and the second electrode.

8. The semiconductor integrated-circuit (IC) chip of claim 7, wherein the oxide layer comprises hafnium oxide (HfO₂).

9. The semiconductor integrated-circuit (IC) chip of claim 7, wherein the insulating layer comprises titanium dioxide.

23. The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a first interconnection metal layer between the first and second layers, wherein the first interconnection metal layer comprises a first metal line having a first copper layer and a first adhesion layer at a bottom and sidewall of the first copper layer, and the first interconnection metal layer has a thickness between 3 and 2,000 nanometers.

24. The semiconductor integrated-circuit (IC) chip of claim 23 further comprising a second interconnection metal layer over the second layer, wherein the second interconnection metal layer comprises a second metal line having a second copper layer and a second adhesion layer at a bottom and sidewall of the second copper layer, and the second interconnection metal layer has a thickness between 3 and 2,000 nanometers.

25. The semiconductor integrated-circuit (IC) chip of claim 3, wherein the magnetoresistive-random-access-memory (MRAM) cell comprises first and second magnetic layers and an oxide layer between the first and second magnetic layers.

26. The semiconductor integrated-circuit (IC) chip of claim 25, wherein the oxide layer comprises magnesium oxide.

27. The semiconductor integrated-circuit (IC) chip of claim 25, wherein the first magnetic layer comprises cobalt (Co), iron (Fe) and boron (B).

10. A semiconductor integrated-circuit (IC) chip comprising:

a semiconductor substrate;

a first layer at a surface of the semiconductor substrate, wherein the first layer comprises a plurality of transistors at the surface of the semiconductor substrate;

a second layer over the first layer and the semiconductor substrate, wherein the second layer comprises a plurality of non-volatile memory cells over the first layer, wherein the plurality of non-volatile memory cells comprises a first memory cell configured to store a programming code;

a sense amplifier configured to sense an input data at a first input point of the sense amplifier by comparing the input data of the sense amplifier with a voltage at a second input point of the sense amplifier to generate an output data at an output point of the sense amplifier, wherein the input data of the sense amplifier is associated with the programming code stored in the first memory cell, wherein the plurality of transistors comprise a plurality of first transistors provided for a plurality of static-random-access-memory (SRAM) cells and a plurality of second transistors provided for a multiplexer, wherein the plurality of static-random-access-memory (SRAM) cells comprises a second memory cell configured to store data associated with the output data at the output point of the sense amplifier, wherein the multiplexer comprises a first set of input points for a first input data set comprising data associated with the data stored in the second memory cell; and

a plurality of interconnects coupling to a second set of input points of the multiplexer for a second input data set of the multiplexer, respectively, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data at an output point of the multiplexer.

11. The semiconductor integrated-circuit (IC) chip of claim 10, wherein the first memory cell comprises a resistive-random-access-memory (RRAM) cell configured to store the programming code.

12. The semiconductor integrated-circuit (IC) chip of claim 10, wherein the first memory cell comprises a magnetoresistive-random-access-memory (MRAM) cell configured to store the programming code.

13. The semiconductor integrated-circuit (IC) chip of claim 10 comprising a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

14. The semiconductor integrated-circuit (IC) chip of claim 10 further comprising a transistor configured to control connection between the first memory cell and the first input point of the sense amplifier based on a voltage level at a gate terminal of the transistor.

15. The semiconductor integrated-circuit (IC) chip of claim 10, wherein the first memory cell comprises a self-select (SS) resistive random access memory (RRAM) cell configured to pass electric current therethrough based on a bias between two ends thereof, wherein one of the two ends of the self-select (SS) resistive random access memory (RRAM) cell couples to the first input point of the sense amplifier.

16. The semiconductor integrated-circuit (IC) chip of claim 15, wherein the self-select (SS) resistive random access memory (RRAM) cell comprises first and second electrodes, an oxide layer between the first and second electrodes and an insulating layer between the oxide layer and the second electrode.

17. The semiconductor integrated-circuit (IC) chip of claim 16, wherein the oxide layer comprises hafnium oxide (HfO₂).

18. The semiconductor integrated-circuit (IC) chip of claim 16, wherein the insulating layer comprises titanium dioxide.

19. The semiconductor integrated-circuit (IC) chip of claim 10 further comprising a first interconnection metal layer between the first and second layers, wherein the first interconnection metal layer comprises a first metal line having a first copper layer and a first adhesion layer at a bottom and sidewall of the first copper layer, wherein the first metal line has a thickness between 3 and 2,000 nanometers.

20. The semiconductor integrated-circuit (IC) chip of claim 19 further comprising a second interconnection metal layer over the second layer, wherein the second interconnection metal layer comprises a second metal line having a second copper layer and a second adhesion layer at a bottom and sidewall of the second copper layer, wherein the second metal line has a thickness between 3 and 2,000 nanometers.

21. The semiconductor integrated-circuit (IC) chip of claim 12, wherein the magnetoresistive-random-access-memory (MRAM) cell comprises first and second magnetic layers and an oxide layer between the first and second magnetic layers.

22. The semiconductor integrated-circuit (IC) chip of claim 21, wherein the magnetoresistive-random-access-memory (MRAM) cell further comprises an antiferromagnetic layer, wherein the first magnetic layer is between the oxide layer and the antiferromagnetic layer.