Multi-stage sampler with increased gain

• US 10,608,847 B2
• Filed: 02/05/2019
• Issued: 03/31/2020
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Neff, Michael R
• Application Number:
  US16/268,303
• Publication Number:
  US 20190182081A1
• Time in Patent Office: 420 Days
• Field of Search: 375229
• CPC Class Codes: H04L 2025/03445 Time domain
• CPC Class Codes: H04L 2025/03522 Frequency domain
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03267 with decision feedback equalisers
• CPC Class Codes: H04L 25/03286 with channel-decoding circuitry
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

Generating first and second discharge control signals in response to a clock signal and an input voltage signal, the first and second discharge control signals decreasing at different rates to a threshold level during a first time period, wherein a difference in rates is determined by the input voltage signal, generating a differential voltage on a pair of nodes during the first time period by selectively controlling a respective amount of discharge of an initial charge on each node of the pair of nodes by applying the first and second discharge control signals to respective transistors in a differential transistor pair connected to the pair of nodes, and maintaining the differential voltage on the pair of nodes during a subsequent time period, and generating an amplified differential voltage during at least a portion of the subsequent time period by amplifying the differential voltage.

Claims

1. An apparatus comprising:

a memory device configured to store one or more historical data values;

a Decision-Feedback Equalization (DFE) computation circuit configured to generate a differential DFE magnitude value;

a decision-feedback offset generator configured to receive the differential DFE magnitude value at a first and a second differential pair of transistors and a historical data value of the one or more historical data values, and to responsively generate an analog DFE correction value having a voltage magnitude equal to the differential DFE magnitude value and a polarity determined via a selection of the first or the second differential pair of transistors according to the historical data value received from the memory device;

an input differential transistor pair configured to receive an analog input signal and to responsively generate an analog output signal; and

a pair of common output nodes connecting differential outputs of the decision-feedback offset generator and the input differential transistor pair, the pair of common output nodes configured to form an analog summation of the analog DFE correction value and the analog output signal.

2. The apparatus of claim 1, wherein the analog input signal is an analog voltage output received from a cascaded analog sampler.

3. The apparatus of claim 1, wherein the analog input signal corresponds to an analog voltage output of a multi-input comparator.

4. The apparatus of claim 1, wherein the first and second differential pairs of the decision-feedback offset generator are further configured to receive a high-frequency injection of the analog input signal.

5. The apparatus of claim 4, wherein the high-frequency injection of the analog input signal is received via a resistor-capacitor high-pass filter.

6. The apparatus of claim 1, wherein the first and second differential pairs of the decision-feedback offset generator are further configured to receive a voltage offset signal.

7. The apparatus of claim 6, wherein the voltage offset signal is associated with a sampler offset value.

8. The apparatus of claim 1, wherein the memory device comprises a shift register.

9. The apparatus of claim 1, further comprising a reset circuit configured to pre-charge the pair of common output nodes according to a sampling clock.

10. The apparatus of claim 9, wherein the analog summation of the analog DFE correction value and the analog output signal is formed responsive to the sampling clock.

11. A method comprising:

obtaining (i) a historical data value from a memory device storing one or more historical data values and (ii) a differential DFE magnitude value from a Decision-Feedback Equalization (DFE) computation circuit;

providing the differential DFE magnitude value to a first and a second differential pair of transistors of a decision-feedback offset generator, and responsively generating an analog DFE correction value having a voltage magnitude equal to the differential DFE magnitude value and a polarity determined via a selection of the first or the second differential pair of transistors by the historical data value;

receiving an analog input signal at an input differential pair of transistors and responsively generating an analog output signal; and

generating an analog summation of the analog DFE correction value and the analog output signal on a pair of common output nodes connecting differential outputs of the decision-feedback offset generator and the input differential pair of transistors.

12. The method of claim 11, wherein the analog input signal is an analog voltage output received from a cascaded analog sampler.

13. The method of claim 11, wherein the analog input signal corresponds to an analog voltage output of a multi-input comparator.

14. The method of claim 11, further comprising receiving a high-frequency injection of the analog input signal at the first and second differential pairs of the decision-feedback offset generator.

15. The method of claim 14, wherein the high-frequency injection of the analog input signal is received via a resistor-capacitor high-pass filter.

16. The method of claim 11, further comprising receiving a voltage offset signal at the first and second differential pairs of the decision-feedback offset generator.

17. The method of claim 16, wherein the voltage offset signal is associated with a sampler offset value.

18. The method of claim 11, wherein the memory device comprises a shift register.

19. The method of claim 11, further comprising pre-charging the pair of common output nodes according to a sampling clock using a reset circuit.

20. The method of claim 19, wherein the analog summation of the analog DFE correction value and the analog output signal is formed responsive to the sampling clock.