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Triple-pass execution using a retire queue having a functional unit to independently execute long latency instructions and dependent instructions

  • US 10,613,859 B2
  • Filed: 08/18/2016
  • Issued: 04/07/2020
  • Est. Priority Date: 08/18/2016
  • Status: Active Grant
First Claim
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1. A microprocessor including an extended pipeline stage comprising:

  • a main execution pipeline processing instructions and configured to forward long latency instructions to a retire queue, the main execution pipeline including an arithmetic logic unit (ALU), the long latency instructions being instructions taking more than one cycle to execute; and

    the retire queue configured to store and execute the long latency instructions and third-pass instructions, wherein one or more of the third-pass instructions have data dependencies upon the long latency instructions, and wherein the third-pass instructions are determined to, when executed, not cause any exception events, the retire queue further comprising;

    a graduate buffer configured to store the long latency instructions;

    a reservation station configured to store the third-pass instructions and dependency indications of the third-pass instructions on the long latency instructions stored in the graduate buffer; and

    a third-pass functional unit configured to receive result data of the long latency instructions and to execute the third-pass instructions using the result data, processing of the third-pass instructions being executed independently from the instructions in the main execution pipeline, wherein the third-pass functional unit comprises one or more additional ALUs separate from the main execution pipeline and the one or more additional ALUs execute the third-pass instructions.

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