Computer architecture

• US 10,613,860 B2
• Filed: 11/09/2016
• Issued: 04/07/2020
• Est. Priority Date: 11/09/2016
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Belliard, Vincent Roger Maurice
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US15/347,768
• Publication Number:
  US 20180129437A1
• Time in Patent Office: 1,245 Days
• Field of Search: 711170
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 9/3001 Arithmetic instructions

Abstract

A tagged memory organized is into memory chunks. Each memory chunk has a data field, a type field and an owner address field. The type field indicates type of data stored in the data field. The owner address field indicates which objects own which memory chunks. A memory manager has exclusive ability to allocate the memory chunks, deallocate the memory chunks, write to the memory chunks and read the memory chunks.

Claims

1. A memory system, comprising:

a tagged memory organized into memory chunks, each memory chunk having an associated memory chunk address field for addressing the memory chunk and each memory chunk further including the following fields;

a data field,

a type field that indicates type of data stored in the data field, and

an owner address tag field that indicates which objects own which memory chunks, wherein an object in the tagged memory owns a plurality of memory chunks that are sequentially organized within the tagged memory and wherein the owner address tag field of said at least one object and the associated memory chunk address field of the first memory chunk in said sequentially arranged plurality of memory chunks have a same value; and

a memory manager that has exclusive ability to allocate the object which comprises said sequentially arranged plurality of memory chunks, deallocate the sequentially arranged plurality of memory chunks, write to the sequentially arranged plurality of memory chunks, and read the sequentially arranged plurality of memory chunks,

wherein when a processor requests access to the object allocated in the tagged memory using an object address and an object offset within the object, the memory manager is configured to;

generate an address of a memory chunk in the tagged memory for access to the object based on the object address and the object offset;

check whether a value in the owner address tag field of the addressed memory chunk is the same as the generated memory chunk address;

grant the access to the object when the value in the owner address tag field of the addressed memory chunk is the same as the generated memory chunk address; and

prevent the access to the object when the value in the owner address tag field of the addressed memory chunk is different from the generated memory chunk address.

2. A memory system as in claim 1, wherein when the processor performs a write operation to a memory location within the tagged memory by providing to the memory manager an object address and an object offset within the object, the memory manager is configured to translate the object address and the object offset into a chunk address for the memory location within the tagged memory in order to perform the write operation.

3. A memory system as in claim 2, wherein when the chunk address for the memory location as translated by the memory manager is not within a memory chunk owned by the object, the memory manager is configured not to perform the write operation and instead raise an exception.

4. A memory system as in claim 1, wherein when the processor performs a read operation from a memory location within the tagged memory by providing to the memory manager an object address and an object offset within the object, the memory manager is configured to translate the object address and the object offset into a chunk address for the memory location within the tagged memory in order to perform the read operation.

5. A memory system as in claim 4, wherein when the chunk address for the memory location as translated by the memory manager is not within a memory chunk owned by the object, the memory manager is configured not to perform the read operation and instead raise an exception.

6. A memory system as in claim 1, wherein when an object is an owner of a plurality of memory chunks, each memory chunk in the plurality of memory chunks having a value in the owner address field that is equal to an address for the object within the tagged memory.

7. A memory system as in claim 1, wherein the data field comprises a plurality of object fields, and wherein the type field indicates a type and a size of each of said object fields.

8. A memory system as in claim 7, wherein the memory manager is further configured to calculate an address in the tagged memory for a requested data, determine whether the calculated address aligns with an object field in the data field in accordance with the corresponding type field, and return an error when it is determined that the calculated address does not align.

9. A memory system as in claim 1, wherein the memory manager is further configured to write a first plurality of object fields in the data field of a first chunk of the object according to a first alignment of object fields indicated in the type field of the first chunk, and a second plurality of object fields in the data field of a second chunk of the object according to a second alignment of object fields indicated in the type field of the first chunk, wherein the first alignment of fields is different from the second alignment of fields.

10. A memory system as in claim 1, wherein the memory manager is further configured to synthesize an instruction by retrieving an address stored in a register and writing the instruction including the retrieved address, a type retrieved from the register, and an opcode, and writing the synthesized instruction to the tagged memory.

11. A computing system comprising:

a tagged memory organized into memory chunks, each memory chunk having an associated memory chunk address field for addressing the memory chunk and each memory chunk further including the following fields;

a data field,

a type field that indicates type of data stored in the data field, and

an owner address field that indicates which objects own which memory chunks, wherein an object in the tagged memory owns a plurality of memory chunks that are sequentially organized within the tagged memory and wherein the owner address tag field of said at least one object and the associated memory chunk address field of the first memory chunk in said sequentially arranged plurality of memory chunks have a same value;

a memory manager that has exclusive ability to allocate the object which comprises said sequentially arranged plurality of memory chunks, write to the sequentially arranged plurality of memory chunks, and read the sequentially arranged plurality of memory chunks;

a plurality of registers, each register having storage capacity to store a value for the data field and a value for the type field; and

a processor configured to use the registers to execute instructions, the instructions specifying functions that can be performed on source arguments that include values in both the data field and the type field,

wherein when a processor requests access to the object allocated in the tagged memory using an object address and an object offset within the object, the memory manager is configured to;

generate an address of a memory chunk in the tagged memory for access to the object based on the object address and the object offset;

check whether a value in the owner address tag field of the addressed memory chunk is the same as the generated memory chunk address;

grant the access to the object when the value in the owner address tag field of the addressed memory chunk is the same as the generated memory chunk address; and

prevent the access to the object when the value in the owner address tag field of the addressed memory chunk is different from the generated memory chunk address.

12. A computing system as in claim 11, wherein the processor is an arithmetic processing unit.

13. A computing system as in claim 11, wherein when the processor performs a write operation to a memory location within the tagged memory by providing to the memory manager an object address and an object offset within the object, the memory manager is configured to translate the object address and the object offset into a chunk address for the memory location within the tagged memory in order to perform the write operation.

14. A computing system as in claim 11, wherein when the processor performs a read operation from a memory location within the tagged memory by providing to the memory manager an object address and an object offset within the object, the memory manager is configured to translate the object address and the object offset into a chunk address for the memory location within the tagged memory in order to perform the read operation.

15. A computing system as in claim 11, wherein the instructions specify functions that can be performed on source arguments of different types so that type of source argument used in execution of the instruction is determined by data type as indicated by a value in the type field of each source argument for the function and not by the instruction itself.

16. A computing system as in claim 11, wherein the type field indicates whether data is an instruction.

17. A computing system as in claim 16, wherein an instruction opcode uses the data field and some bits of the type field.

18. A computing system as in claim 17, wherein the only way to generate an instruction executable in the computing system is by using a special instruction which generates a new instruction.

19. A method for performing memory accesses within a memory system, the method comprising:

organizing a tagged memory into memory chunks, each memory chunk having an associated memory chunk address field for addressing the memory chunk and each memory chunk further including the following fields;

a data field,

a type field, that indicates type of data stored in the data field,

an owner address tag field that indicates which objects own which memory chunks, wherein an object in the tagged memory owns a plurality of memory chunks that are sequentially organized within the tagged memory and wherein the owner address tag field of said at least one object and the associated memory chunk address field of the first memory chunk in said sequentially arranged plurality of memory chunks have a same value;

exclusively using a memory manager to allocate the object which comprises said sequentially arranged plurality of memory chunks in the tagged memory, write to the sequentially arranged plurality of memory chunks, and read the sequentially arranged plurality of memory chunks;

a processor requesting access to the object allocated in the tagged memory using an object address and an object offset within the object; and

in response to the request for access to the object, the memory manager performs the following steps;

generating an address of a memory chunk in the tagged memory for access to the object based on the object address and the object offset;

checking whether a value in the owner address tag field of the addressed memory chunk is the same as the generated memory chunk address;

granting the access to the object when the value in the owner address tag field of the addressed memory chunk is the same as the generated memory chunk address; and

preventing the access to the object when the value in the owner address tag field of the addressed memory chunk is different from the generated memory chunk address.

20. A method as in claim 19, additionally comprising performing a write operation by a processor including:

providing, from the processor to the memory manager, an object address and an object offset within the object,

translating, by the memory manager, the object address and the object offset into an address for the memory location within the tagged memory, and

performing, by the memory manager, the write operation to the memory location by the memory manager.

21. A method as in claim 20, wherein when the address for the memory location as translated by the memory manager is not within a memory chunk owned by the object, the memory manager does not perform the write operation and instead raises an exception.

22. A method as in claim 19, additionally comprising performing a read operation by a processor including:

providing, from the processor to the memory manager, an object address and an object offset within the object,

translating, by the memory manager, the object address and the object offset into a chunk address for the memory location within the tagged memory, and

performing, by the memory manager, the read operation from the memory location by the memory manager.

23. A method as in claim 19, additionally comprising executing an instruction by the processor including:

obtaining source arguments for executing the instruction from a plurality of registers, each register having storage capacity to store a value for the data field and a value for the type field.

24. A method as in claim 23, wherein executing the instruction by the processor additionally includes:

using, by the processor, data type as indicated by a value in the type field of each source argument for the function to determine type of source argument used in execution of the instruction and not using the instruction itself to determine type of source argument used in execution of the instruction.