Apparatus and method for controlling instruction execution behaviour

• US 10,613,865 B2
• Filed: 07/21/2016
• Issued: 04/07/2020
• Est. Priority Date: 08/27/2015
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Barnes, Graeme Peter
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US15/749,806
• Publication Number:
  US 20180225120A1
• Time in Patent Office: 1,356 Days
• Field of Search: None
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/34 Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes address translation G06F12/00
• CPC Class Codes: G06F 9/35 Indirect addressing
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

An apparatus and method are provided for controlling instruction execution behaviour. The apparatus includes a set of data registers for storing data values, and a set of bounded pointer storage elements, where each bounded pointer storage element stores a pointer having associated range information indicative of an allowable range of addresses when using that pointer. A control storage element stores a current instruction context, and that current instruction context is used to influence the behaviour of at least one instruction executed by processing circuitry, that at least one instruction specifying a pointer reference for a required pointer, where the pointer reference is within at least a first subset of values (in one embodiment the behaviour is influenced irrespective of the value of the required pointer). In particular, when the current instruction context identifies a default state, the processing circuitry uses the pointer reference to identify one of the data registers whose stored data value forms the required pointer. However, when the current instruction context identifies a bounded pointer state, the processing circuitry instead uses the pointer reference to identify one of the bounded pointer storage elements whose stored pointer forms the required pointer. This allows an instruction set to be provided that can be used for both bounded pointer aware code and bounded pointer unaware code, without significantly increasing the pressure on instruction set encoding space.

Claims

1. An apparatus, comprising:

a set of bounded pointer storage elements, each bounded pointer storage element to store a pointer having associated range information indicative of an allowable range of addresses when using said pointer;

a set of data registers to store data values;

processing circuitry to execute a sequence of instructions; and

a control storage element to store a current instruction context;

the processing circuitry being responsive to execution of at least one instruction in said sequence that specifies a pointer reference for a required pointer, where the pointer reference is within at least a first subset of values;

to use the pointer reference to identify one of the data registers whose stored data value forms the required pointer, when the current instruction context identifies a default state;

to use the pointer reference to identify one of the bounded pointer storage elements whose stored pointer forms the required pointer, when the current instruction context identifies a bounded pointer state;

to determine an address from the required pointer;

when the current instruction context identifies the bounded pointer state, to perform a bound check operation to check that the determined address is within the allowable range of addresses indicated by the associated range information for said one of the bounded pointer storage elements; and

when the current instruction context identifies the default state, to perform a default bound check operation to check that the determined address is within a default allowable range of addresses.

2. An apparatus as claimed in claim 1, further comprising a default range storage element to store range information indicative of said default allowable range.

3. An apparatus as claimed in claim 1, wherein when performing the bound check operation, the processing circuitry takes into account a size of data value being accessed at the determined address, in order to ensure that all of the data value is within the allowable range of addresses.

4. An apparatus as claimed in claim 1, wherein:

said processing circuitry is responsive to execution of at least one further instruction in said sequence to update the current instruction context stored in said control storage element.

5. An apparatus as claimed in claim 4, wherein:

at least one of the bounded pointer storage elements includes a destination instruction context field specifying an instruction context value;

said at least one further instruction is a branch instruction having, as a specified bounded pointer storage element, one of said at least one of the bounded pointer storage elements; and

the processing circuitry is responsive to executing said branch instruction to update the current instruction context by storing in the control storage element the instruction context value from the specified bounded pointer storage element.

6. An apparatus as claimed in claim 5, further comprising a bounded program counter storage element to store a program counter pointer having associated range information indicative of an allowable range of program counters determined from said program counter pointer, and the processing circuitry is additionally responsive to execution of said branch instruction to update the bounded program counter storage element using the pointer and associated range information of said specified bounded pointer storage element.

7. An apparatus as claimed in claim 5, wherein:

said branch instruction is executable by the processing circuitry in both said default state and said bounded pointer state to allow a switch between said default state and said bounded pointer state.

8. An apparatus as claimed in claim 7, wherein:

said set of bounded pointer storage elements includes a bounded link storage element whose pointer is used to identify a return address, the bounded link storage element further identifying a return instruction context;

said branch instruction specifies said bounded link storage element and is executed by the processing circuitry to return from an earlier branch and to update the current instruction context by storing in the control storage element the return instruction context identified in the bounded link storage element.

9. An apparatus as claimed in claim 4, wherein:

said at least one further instruction comprises an update instruction to write an update value specified by the update instruction into said control storage element in order to update the current instruction context.

10. An apparatus as claimed in claim 9, wherein the update instruction identifies one of said data registers whose stored data value is used to update the current instruction context.

11. An apparatus as claimed in claim 9, wherein the update instruction specifies an immediate value used to update the current instruction context.

12. An apparatus as claimed in claim 1, wherein said at least one instruction in said sequence that specifies a pointer reference for a required pointer is at least one of a load instruction and a store instruction.

13. An apparatus as claimed in claim 1, wherein said processing circuitry is arranged to execute instructions from an instruction set, said instruction set comprising a first subset of instructions whose execution behaviour is independent of said current instruction context, and a second subset of instructions whose execution behaviour is dependent on said current instruction context, said second subset comprising said at least one instruction in said sequence that specifies a pointer reference for a required pointer.

14. An apparatus as claimed in claim 13, wherein said instruction set includes at least one additional instruction that specifies a pointer reference for a required pointer, wherein when executing said at least one additional instruction, the processing circuitry is arranged to use the pointer reference to identify one of the bounded pointer storage elements whose stored pointer forms the required pointer, irrespective of whether the current instruction context identifies the bounded pointer state or the default state.

15. An apparatus as claimed in claim 13, wherein said instruction set includes at least one opposite state behaviour instruction that specifies a pointer reference for a required pointer, wherein when executing said at least one opposite state behaviour instruction, the processing circuitry is arranged

to use the pointer reference to identify one of the data registers whose stored data value forms the required pointer, when the current instruction context identifies the bounded pointer state;

to use the pointer reference to identify one of the bounded pointer storage elements whose stored pointer forms the required pointer, when the current instruction context identifies the default state.

16. An apparatus as claimed in claim 1, wherein said set of bounded pointer storage elements comprise a set of bounded pointer storage registers.

17. An apparatus as claimed in claim 1, wherein each bounded pointer storage element is configured to store the pointer and the associated range information.

18. An apparatus as claimed in claim 1, comprising a further storage element to store the associated range information for the pointer stored in a corresponding bounded pointer storage element.

19. An apparatus as claimed in claim 1, wherein the range information identifies a lower bound and an upper bound for the allowable range of addresses.

20. An apparatus as claimed in claim 1, wherein the range information identifies one of a lower bound and an upper bound for the allowable range of addresses, and a size of the allowable range of addresses.

21. An apparatus as claimed in claim 1, wherein the processing circuitry is responsive to execution of said at least one instruction in said sequence, irrespective of the value of the pointer reference:

to use the pointer reference to identify one of the data registers whose stored data value forms the required pointer, when the current instruction context identifies the default state;

to use the pointer reference to identify one of the bounded pointer storage elements whose stored pointer forms the required pointer, when the current instruction context identifies the bounded pointer state.

22. An apparatus as claimed in claim 1, wherein the processing circuitry is responsive to execution of said at least one instruction in said sequence, when the pointer reference is within a second subset of values different to said first subset, to use the pointer reference to identify one of the data registers whose stored data value forms the required pointer, irrespective of whether the current instruction context identifies the default state or the bounded pointer state.

23. An apparatus as claimed in claim 1, wherein:

said control storage element is arranged to store at least one further current instruction context; and

the processing circuitry is arranged to reference the current instruction context when the pointer reference specified by said at least one instruction is within said first subset of values, and to reference one of said at least one further current instruction contexts when the pointer reference specified by said at least one instruction is within at least one further subset of values;

such that the pointer reference is used to identify either a data register or a bounded pointer storage element dependent on the current instruction context applicable for the value of the pointer reference.

24. A method of controlling instruction execution behaviour within an apparatus having a set of bounded pointer storage elements, each bounded pointer storage element for storing a pointer having associated range information indicative of an allowable range of addresses when using said pointer, and having a set of data registers for storing data values, the method comprising:

storing within a control storage element a current instruction context;

on executing at least one instruction that specifies a pointer reference for a required pointer, where the pointer reference is within at least a first subset of values;

using the pointer reference to identify one of the data registers whose stored data value forms the required pointer, when the current instruction context identifies a default state;

using the pointer reference to identify one of the bounded pointer storage elements whose stored pointer forms the required pointer, when the current instruction context identifies a bounded pointer state;

determining an address from the required pointer;

when the current instruction context identifies the bounded pointer state, performing a bound check operation to check that the determined address is within the allowable range of addresses indicated by the associated range information for said one of the bounded pointer storage elements; and

when the current instruction context identifies the default state, performing a default bound check operation to check that the determined address is within a default allowable range of addresses.

25. An apparatus, comprising:

a set of bounded pointer storage means, each bounded pointer storage means for storing a pointer having associated range information indicative of an allowable range of addresses when using said pointer;

a set of data register means for storing data values;

processing means for executing a sequence of instructions; and

a control storage means for storing a current instruction context;

the processing means, responsive to execution of at least one instruction in said sequence that specifies a pointer reference for a required pointer, where the pointer reference is within at least a first subset of values;

for using the pointer reference to identify one of the data register means whose stored data value forms the required pointer, when the current instruction context identifies a default state;

for using the pointer reference to identify one of the bounded pointer storage means whose stored pointer forms the required pointer, when the current instruction context identifies a bounded pointer state;

for determining an address from the required pointer;

when the current instruction context identifies the bounded pointer state, for performing a bound check operation to check that the determined address is within the allowable range of addresses indicated by the associated range information for said one of the bounded pointer storage means; and

when the current instruction context identifies the default state, for performing a default bound check operation to check that the determined address is within a default allowable range of addresses.