Peer-to-peer non-volatile random-access memory

• US 10,613,974 B2
• Filed: 04/28/2017
• Issued: 04/07/2020
• Est. Priority Date: 10/04/2016
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Dreier, Roland, Karr, Ronald, Kirkpatrick, Peter E.
• Primary Examiner(s): Choe, Yong J
• Application Number:
  US15/582,381
• Publication Number:
  US 20180095871A1
• Time in Patent Office: 1,075 Days
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: H04L 67/104 Peer-to-peer [P2P] networks
• CPC Class Codes: H04L 67/1095 Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

A system may include embedded storage devices, each including an addressable non-volatile random-access memory (NVRAM) portion and storage system controllers operatively coupled to the embedded storage devices via a full-duplex switched network. The storage system controllers may be configured to instruct a first embedded storage device of the plurality of embedded storage devices to: receive first data to be stored in a first NVRAM portion of the embedded storage device, store the first data in the first NVRAM portion of the first embedded storage device, and send second data to a second NVRAM portion of a second embedded storage device directly via the full-duplex switched network.

Claims

1. A storage system comprising:

a plurality of embedded storage devices each comprising an addressable non-volatile random-access memory (NVRAM) portion; and

a plurality of storage system controllers, operatively coupled to the plurality of embedded storage devices via a full-duplex switched network, the plurality of storage system controllers to instruct a first embedded storage device of the plurality of embedded storage devices to;

receive first data to be stored in a first NVRAM portion of the first embedded storage device;

store the first data in the first NVRAM portion of the first embedded storage device;

send second data, associated with the first data, to a second NVRAM portion of a second embedded storage device of the plurality of embedded storage devices directly via the full-duplex switched network, wherein the first NVRAM portion and the second NVRAM portion are direct-mapped and separately addressable;

receive third data to be stored in the first NVRAM portion of the embedded storage device;

calculate an erasure code corresponding to the third data;

store a first portion of the erasure code in the first NVRAM portion of the first embedded storage device; and

send a second portion of the erasure code to the second NVRAM portion of a second embedded storage device of the plurality of embedded storage devices directly via the full-duplex switched network.

2. The storage system of claim 1, wherein the second data is a copy of the first data.

3. The storage system of claim 1, wherein the first data is a first portion of an erasure code corresponding to third data and wherein the second data is a second portion of the erasure code corresponding to the third data.

4. The storage system of claim 1, wherein the plurality of storage system controllers are further to instruct the second embedded storage device to:

send, in response to storing the second data in the second NVRAM portion of the second embedded storage device, an indication that the second data was stored in the second NVRAM portion of the second embedded storage device directly to the plurality of storage system controllers.

5. The storage system of claim 1, wherein the NVRAM portion comprises a random-access memory (RAM) device, a processing device, and a capacitor, the plurality of storage system controllers to instruct a first embedded storage device of the plurality of embedded storage devices to:

detect a power failure associated with the first embedded storage device; and

in response to detecting the power failure, copy the first data stored in the first NVRAM portion to a local flash storage portion of the first embedded storage device using electricity from the capacitor.

6. A method comprising:

receiving, by a processing device of a first storage device, from a second storage device, first data to be stored in a first non-volatile random-access memory (NVRAM) portion of the first storage device;

storing, by the processing device, the first data in the first NVRAM portion of the first storage device;

sending, by the processing device, second data, associated with the first data, to a second NVRAM portion of a second storage device directly via a communication network;

receiving third data to be stored in the first NVRAM portion of the first storage device;

calculating an erasure code corresponding to the third data;

storing a first portion of the erasure code in the first NVRAM portion of the first storage device; and

sending a second portion of the erasure code to the second NVRAM portion of a second storage device directly via the communication network.

7. The method of claim 6, wherein the second data is a copy of the first data.

8. The method of claim 7, wherein the communication network is one of:

a full-duplex switched network, a mesh network, a cross-connect, or direct point-to-point interconnection.

9. The method of claim 6, wherein the first data is a first portion of an erasure code corresponding to third data and wherein the second data is a second portion of the erasure code corresponding to the third data.

10. The method of claim 6, further comprising:

sending, in response to storing the first data in the first NVRAM portion of the first storage device, an indication that the first data was stored in the first NVRAM portion of the first storage device directly to a storage controller associated with the second storage device.

11. The method of claim 6, wherein the first NVRAM portion comprises a random-access memory (RAM) device, a processing device, and a capacitor.