Target port with distributed transactions

• US 10,613,977 B1
• Filed: 09/27/2018
• Issued: 04/07/2020
• Est. Priority Date: 09/27/2018
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Diamant, Ron, Huang, Randy Renfu
• Primary Examiner(s): Dudek, Jr., Edward J
• Application Number:
  US16/145,135
• Time in Patent Office: 558 Days
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence

Abstract

Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, the integrated circuit device can include a target port operable to receive transactions from master ports. The target port can be configured with a multicast address range that is associated with a plurality of indices corresponding to memory banks of the device. When the target port receives a write transaction that has an address that is within the multicast address range, the target port can determine an index from the plurality of indices, and can use the index to determine a second address, which combines the index and the offset value with the address. The target port can then use the second address to write the data to the memory.

Claims

1. An integrated circuit device, comprising:

a computational array circuit operable to perform a systolic array computation;

a memory coupled to the computational array circuit, the memory including a plurality of banks, wherein the memory is configured to input data into the computational array circuit;

an integrated circuit component implementing a target port, wherein the target port is coupled to a first bus for receiving read and write transactions from a first master port and a second bus for receiving read and write transactions from a second master port, wherein the target port is configured with a first multicast address range, wherein the first multicast address range is associated with a plurality of indices corresponding to banks from the plurality of banks; and

wherein the target port is operable to;

receive a write transaction for the memory, the write transaction including an address, data, and an offset value;

determine that the address is within the first multicast address range;

select an index from the plurality of indices, wherein the plurality of indices are selected sequentially;

determine a second address by combining the index and the offset value and adding a result to the address; and

writing the data to the memory using the second address, wherein using the second address shifts the data from a location indicated by the address.

2. The integrated circuit device of claim 1, wherein the target port is further configured with a second multicast address range, wherein the second multicast address range is associated with a different plurality of indices corresponding to different banks from the plurality of banks.

3. The integrated circuit device of claim 1, wherein the offset value indicates a number of data words in the data and the index indicates a bank from the plurality of banks, such that, when the plurality of banks is read at a same offset, a copy of the data output from each bank in a column of banks is staggered relative to other banks from the column of banks.

4. The integrated circuit device of claim 1, wherein the offset value is included in a field of the write transaction whose use is not specified by a bus protocol implemented by the target port.

5. An integrated circuit device, comprising:

a computational array circuit;

a memory coupled to the computational array circuit, the memory including a plurality of banks, wherein the memory is configured to input data into the computational array circuit;

a target port operable to receive read and write transactions from a plurality of master ports, wherein the target port has point-to-point connections with the plurality of master ports, wherein the target port is configured with a multicast address range, wherein the multicast address range is associated with a plurality of indices corresponding to banks from the plurality of banks; and

wherein the target port is operable to;

receive a write transaction for the memory, the write transaction including an address, data, and an offset value;

determine that the address is within the multicast address range;

determine an index from the plurality of indices;

determine a second address by combining the index and the offset value and adding a result to the address; and

write the data to the memory using the second address, wherein using the second address shifts the data from a location indicated by the address.

6. The integrated circuit device of claim 5, wherein the index is determined from a count of write transactions received for the address.

7. The integrated circuit device of claim 5, wherein the index is determined from the address.

8. The integrated circuit device of claim 5, wherein the index is provided in a field of the write transaction.

9. The integrated circuit device of claim 5, wherein the index is determined from a count of writes to the memory generated by the write transaction.

10. The integrated circuit device of claim 5, wherein the target port is further operable to:

duplicate the write transaction for each index from the plurality of indices, wherein duplicating the write transaction causes the data to be written to multiple banks of the memory.

11. The integrated circuit device of claim 10, wherein, for each index, the data is shifted from the location indicated by the address by a different amount.

12. The integrated circuit device of claim 10, wherein the target port is further operable to:

generate one completion response upon completing writing of the data to the multiple banks of the memory.

13. The integrated circuit device of claim 5, wherein the target port is further operable to:

transmit, upon writing of the data completing, a completion response to the write transaction.

14. The integrated circuit device of claim 5, wherein the plurality of banks each input data into different rows from the computational array circuit.

15. The integrated circuit device of claim 5, wherein the integrated circuit device is operable to:

read copies of the data from banks from the plurality of banks; and

input the copies of the data into the computational array circuit for the computational array circuit to compute a result.

16. The integrated circuit device of claim 5, wherein a point-to-point connection is a bus structure on which the target port communicates with only one master port of the integrated circuit device.

17. The integrated circuit device of claim 5, further comprising:

a set of registers operable to store values describing the multicast address range;

a comparison circuit operable to use the values stored in the set of registers to determine whether a particular address is in the multicast address range; and

a transaction management circuit operable to receive the write transaction, determine the index, and write the data to the memory.

18. A method for operating an integrated circuit device, comprising:

receiving, at a target port of the integrated circuit device, a write transaction for a memory of the integrated circuit device, the write transaction including an address, data, and an offset value, wherein the memory includes a plurality of banks, wherein the target port has point-to-point connections with a plurality of master ports, wherein the target port is configured with a multicast address range, wherein the multicast address range is associated with a plurality of indices corresponding to banks from the plurality of banks;

determining that the address is in the multicast address range;

determining a first index from the plurality of indexes;

determining a second address by combining the first index and the offset value and adding a result to the address; and

writing the data to the memory using the second address, wherein using the second address shifts the data from a location indicated by the address.

19. The method of claim 18, further comprising:

receiving, at the target port, a second write transaction for the memory, the second write transaction including a third address;

determining that the second address is not in the multicast address range; and

writing the data to the memory using the second address.

20. The method of claim 18, further comprising:

receiving, at the target port, a second write transaction for the memory, the second write transaction including the address, the data, and the offset value;

determining a second index from the plurality of indices, wherein the second index is different from the first index;

determining a third address by combining the second index and the offset value and adding a result to the address; and

writing the data to the memory using the third address, wherein using the third address shifts the data by a different amount from the location indicated by the address.

21. The method of claim 20, further comprising:

transmitting, upon completion of writing of the data using the second address, a first completion response to the write transaction; and

transmitting, upon completion of writing of the data using the third address, a second completion response to the second write transaction.