Target port with distributed transactions
First Claim
1. An integrated circuit device, comprising:
- a computational array circuit operable to perform a systolic array computation;
a memory coupled to the computational array circuit, the memory including a plurality of banks, wherein the memory is configured to input data into the computational array circuit;
an integrated circuit component implementing a target port, wherein the target port is coupled to a first bus for receiving read and write transactions from a first master port and a second bus for receiving read and write transactions from a second master port, wherein the target port is configured with a first multicast address range, wherein the first multicast address range is associated with a plurality of indices corresponding to banks from the plurality of banks; and
wherein the target port is operable to;
receive a write transaction for the memory, the write transaction including an address, data, and an offset value;
determine that the address is within the first multicast address range;
select an index from the plurality of indices, wherein the plurality of indices are selected sequentially;
determine a second address by combining the index and the offset value and adding a result to the address; and
writing the data to the memory using the second address, wherein using the second address shifts the data from a location indicated by the address.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, the integrated circuit device can include a target port operable to receive transactions from master ports. The target port can be configured with a multicast address range that is associated with a plurality of indices corresponding to memory banks of the device. When the target port receives a write transaction that has an address that is within the multicast address range, the target port can determine an index from the plurality of indices, and can use the index to determine a second address, which combines the index and the offset value with the address. The target port can then use the second address to write the data to the memory.
-
Citations
21 Claims
-
1. An integrated circuit device, comprising:
-
a computational array circuit operable to perform a systolic array computation; a memory coupled to the computational array circuit, the memory including a plurality of banks, wherein the memory is configured to input data into the computational array circuit; an integrated circuit component implementing a target port, wherein the target port is coupled to a first bus for receiving read and write transactions from a first master port and a second bus for receiving read and write transactions from a second master port, wherein the target port is configured with a first multicast address range, wherein the first multicast address range is associated with a plurality of indices corresponding to banks from the plurality of banks; and
wherein the target port is operable to;receive a write transaction for the memory, the write transaction including an address, data, and an offset value; determine that the address is within the first multicast address range; select an index from the plurality of indices, wherein the plurality of indices are selected sequentially; determine a second address by combining the index and the offset value and adding a result to the address; and writing the data to the memory using the second address, wherein using the second address shifts the data from a location indicated by the address. - View Dependent Claims (2, 3, 4)
-
-
5. An integrated circuit device, comprising:
-
a computational array circuit; a memory coupled to the computational array circuit, the memory including a plurality of banks, wherein the memory is configured to input data into the computational array circuit; a target port operable to receive read and write transactions from a plurality of master ports, wherein the target port has point-to-point connections with the plurality of master ports, wherein the target port is configured with a multicast address range, wherein the multicast address range is associated with a plurality of indices corresponding to banks from the plurality of banks; and
wherein the target port is operable to;receive a write transaction for the memory, the write transaction including an address, data, and an offset value; determine that the address is within the multicast address range; determine an index from the plurality of indices; determine a second address by combining the index and the offset value and adding a result to the address; and write the data to the memory using the second address, wherein using the second address shifts the data from a location indicated by the address. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A method for operating an integrated circuit device, comprising:
-
receiving, at a target port of the integrated circuit device, a write transaction for a memory of the integrated circuit device, the write transaction including an address, data, and an offset value, wherein the memory includes a plurality of banks, wherein the target port has point-to-point connections with a plurality of master ports, wherein the target port is configured with a multicast address range, wherein the multicast address range is associated with a plurality of indices corresponding to banks from the plurality of banks; determining that the address is in the multicast address range; determining a first index from the plurality of indexes; determining a second address by combining the first index and the offset value and adding a result to the address; and writing the data to the memory using the second address, wherein using the second address shifts the data from a location indicated by the address. - View Dependent Claims (19, 20, 21)
-
Specification