Processor core to coprocessor interface with FIFO semantics

• US 10,614,023 B2
• Filed: 06/28/2019
• Issued: 04/07/2020
• Est. Priority Date: 09/06/2016
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Brown, David A., Fowler, Daniel, Jain, Rishabh, Schlanger, Erik, Duller, Michael
• Primary Examiner(s): Shin, Christopher B
• Application Number:
  US16/457,793
• Publication Number:
  US 20190324939A1
• Time in Patent Office: 284 Days
• Field of Search: 710105
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Claims

1. A method comprising:

storing an unallocated linked list that contains a first plurality of content nodes that initially do not contain content for a first-in first-out (FIFO) of pending work for a second processor;

storing, in a first content node of the first plurality of content nodes, a pointer that points to a second content node of the first plurality of content nodes;

storing an allocated linked list that contains a second plurality of content nodes that contain content for the FIFO;

sending, by a first processor, a first hardware signal that indicates that content is available for appending onto the FIFO, wherein said content comprises a memory pointer that identifies, or a descriptor that describes, a unit of work for the second processor;

in response to said first hardware signal;

assigning a second pointer, in a third content node in the second plurality of content nodes that contain content for the FIFO in the allocated linked list, to point to the second content node, and

copying said content into said second content node;

sending, by the second processor, a second hardware signal that indicates that said content is transferred into said FIFO,

wherein the method is performed by a computing device that contains the FIFO, the first processor, and the second processor.

2. The method of claim 1 wherein

said second pointer comprises:

a memory address or an array offset.

3. The method of claim 2 wherein:

said second pointer cannot be directly modified by software, and/or

the array offset consumes;

less space than a memory address, at most one byte, and/or less than one byte.

4. The method of claim 1 wherein said second content node cannot be directly modified by software.

5. The method of claim 1 wherein

the allocated linked list and the unallocated linked list are a same linked list.

6. The method of claim 5

further comprising removing a fourth content node from said same linked list during said assigning the second pointer to point to the second content node.

7. The method of claim 1:

further comprising removing a fourth content node from the unallocated linked list during said assigning the second pointer to point to the second content node.

8. A method comprising:

a second processor

blocking said second processor until a first-in first-out (FIFO) contains an amount of content that exceeds a software-configurable threshold;

sending, by a first processor, a first hardware signal that indicates that content is available for appending said FIFO;

in response to said first hardware signal, transferring said content into said FIFO by a computing device that contains the FIFO, the first processor, and the second processor;

sending, by said second processor, a second hardware signal that indicates that said content is transferred into said FIFO.

9. The method of claim 8 further comprising a third processor blocking while attempting to send same said first hardware signal until said sending said second hardware signal.

10. The method of claim 9 wherein said third processor blocking is in response to:

selecting, at random, the third processor for said blocking,

selecting, by round robin, the third processor for said blocking,

the first processor initiating said sending the first hardware signal before the third processor initiates said attempting to send same said first hardware signal, or

the first processor initiating said sending the first hardware signal after the third processor initiates said attempting to send same said first hardware signal.

11. The method of claim 9 wherein:

the third processor contains a first execution thread and a second execution thread;

said third processor blocking comprises task switching from the first execution thread to the second execution thread.

12. The method of claim 8 wherein said transferring said content into said FIFO does not occur until the FIFO is not full.

13. The method of claim 8 wherein:

said FIFO is a first FIFO;

the first FIFO and a second FIFO do not have a fixed size;

the first FIFO and the second FIFO compete for space in a same shared memory.

14. One or more non-transitory computer-readable media storing instructions that, when executed by one or more processors, cause:

storing an unallocated linked list that contains a first plurality of content nodes that initially do not contain content for a first-in first-out (FIFO) of pending work for a second processor;

storing, in a first content node of the first plurality of content nodes, a pointer that points to a second content node of the first plurality of content nodes;

storing an allocated linked list that contains a second plurality of content nodes that contain content for the FIFO;

sending, by a first processor, a first hardware signal that indicates that content is available for appending onto the FIFO, wherein said content comprises a memory pointer that identifies, or a descriptor that describes, a unit of work for the second processor;

in response to said first hardware signal;

assigning a second pointer, in a third content node in the second plurality of content nodes that contain content for the FIFO in the allocated linked list, to point to the second content node, and

copying said content into said second content node;

sending, by the second processor, a second hardware signal that indicates that said content is transferred into said FIFO.

15. The one or more non-transitory computer-readable media of claim 14 wherein said second content node cannot be directly modified by software.

16. The one or more non-transitory computer-readable media of claim 14 wherein

the allocated linked list and the unallocated linked list are a same linked.

17. The one or more non-transitory computer-readable media of claim 14 wherein

the instructions further cause removing a fourth content node from the unallocated linked list during said assigning the second pointer to point to the second content node.

18. One or more non-transitory computer-readable media storing instructions that, when executed by one or more processors, cause:

a second processor

blocking said second processor until said FIFO contains an amount of content that exceeds a software-configurable threshold;

sending, by a first processor, a first hardware signal that indicates that content is available for appending said FIFO;

in response to said first hardware signal, transferring said content into said FIFO;

sending, by said second processor, a second hardware signal that indicates that said content is transferred into said FIFO.

19. The one or more non-transitory computer-readable media of claim 18 wherein the instructions further cause a third processor blocking while attempting to send same said first hardware signal until said sending said second hardware signal.

20. The one or more non-transitory computer-readable media of claim 18 wherein:

said FIFO is a first FIFO;

the first FIFO and a second FIFO do not have a fixed size;

the first FIFO and the second FIFO compete for space in a same shared memory.