Display device and method of driving the same

• US 10,614,740 B2
• Filed: 09/27/2016
• Issued: 04/07/2020
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Junho, Lee, Youngjang
• Primary Examiner(s): Flores, Roberto W
• Application Number:
  US15/277,194
• Publication Number:
  US 20170092178A1
• Time in Patent Office: 1,288 Days
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/067 Special waveforms for scanning, where no circuit details of the gate driver are given
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2340/16 Determination of a pixel data signal depending on the signal applied in the previous frame
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

Provided are a display device and method of driving the same. A display device includes: a display panel including: data lines and gate lines intersecting each other, and pixels in a matrix, a timing controller configured to reduce a refresh rate of the pixels in a low-speed driving mode compared to a refresh rate of the pixels in a normal driving mode, and a display panel driving circuit configured to: write data to the display panel, write data to the pixels during N driving frame periods within a unit of time, that is set to the refresh rate of the low-speed driving mode, under the control of the timing controller, where “N” is a positive integer of 2 to 4, wherein the pixels are configured to hold a voltage of previous data for a remaining time other than the N driving frame periods of the unit of time.

Claims

1. A display device, comprising:

a display panel comprising;

data lines and gate lines intersecting each other; and

pixels in a matrix;

a timing controller configured to reduce a refresh rate of the pixels in a low-speed driving mode compared to a refresh rate of the pixels in a normal driving mode; and

a display panel driving circuit configured to;

write data to the display panel;

write data to the pixels during N driving frames within a unit of time, that is set to the refresh rate of the low-speed driving mode, under the control of the timing controller, where “

N”

is a positive integer of 2 to 4,

wherein the pixels are configured to hold a voltage of previous data for a remaining time other than the N driving frames of the unit of time,

wherein a driving frame period of the low-speed driving mode includes at least two driving frames arranged in a time interval of one frame period,

wherein a frame period between the driving frame periods is a hold frame period during which pixels are not driven, and

wherein the timing controller varies the number of driving frames in which the pixels are driven and emit light, based on both an average grey level of each frame data and a difference in the average gray level between data of adjacent two frames.

2. The display device of claim 1, wherein:

when the average gray level of each frame data is equal to or less than a predetermined first threshold value in the low-speed driving mode, the timing controller assigns two driving frames within the unit of time of the low-speed driving mode;

when the average gray level of each frame data is greater than the first threshold value in the low-speed driving mode, and the difference in the average gray level between previous frame data and current frame data is less than a predetermined second threshold value, the timing controller assigns two driving frames within the unit of time of the low-speed driving mode; and

when the average gray level of each frame data is greater than the first threshold value in the low-speed driving mode, and the difference in the average gray level between the previous frame data and the current frame data is equal to or greater than the second threshold value, the timing controller assigns three driving frames within the unit of time of the low-speed driving mode.

3. The display device of claim 1, wherein each pixel comprises an oxide transistor.

4. The display device of claim 1, wherein each pixel comprises:

an oxide transistor; and

a polycrystalline silicon transistor.

5. A method of driving a display device comprising a display panel, comprising data lines and gate lines intersecting each other and pixels in a matrix, and a display panel driving circuit for writing data to the display panel, the method comprising:

reducing a refresh rate of the pixels in a low-speed driving mode compared to a refresh rate of the pixels in a normal driving mode;

writing data to the pixels during N driving frames within a unit of time that is set to the refresh rate of the low-speed driving mode, where “

N”

is a positive integer of 2 to 4; and

holding the pixels at a voltage of previous data for a remaining time other than the N driving frames of the unit of time,

wherein a driving frame period of the low-speed driving mode includes at least two driving frames arranged in a time interval of one frame period,

wherein a frame period between the driving frame periods is a hold frame period during which pixels are not driven, and

wherein the writing of the data to the pixels during the N driving frames comprises varying the number of driving frames in which the pixels are driven, based on both an average grey level of each frame data and a difference in the average gray level between data of adjacent two frames.

6. The method of claim 5, wherein the reducing of the refresh rate of the pixels in the low-speed driving mode compared to the refresh rate of the pixels in the normal driving mode comprises:

when the average gray level of each frame data is equal to or less than a predetermined first threshold value in the low-speed driving mode, assigning two driving frames within the unit of time of the low-speed driving mode;

when the average gray level of each frame data is greater than the first threshold value in the low-speed driving mode, and the difference in the average gray level between previous frame data and current frame data is less than a predetermined second threshold value, assigning two driving frames within the unit of time of the low-speed driving mode; and

when the average gray level of each frame data is greater than the first threshold value in the low-speed driving mode, and the difference in the average gray level between the previous frame data and the current frame data is equal to or greater than the second threshold value, assigning three driving frames within the unit of time of the low-speed driving mode.

7. An apparatus, comprising:

a controller configured to provide timing control signals to a display panel including a pixel matrix operating in a normal driving mode and in a low-speed driving mode, the display panel including one or more first type TFTs with an oxide semiconductor active layer in a bottom-gate structure and one or more second type TFTs with a polycrystalline silicon active layer in a top-gate structure,

wherein the controller is further configured to;

calculate an average grey level of each frame data and a difference in the average gray level between data of adjacent two frames in the low-speed driving mode, and

vary a number of frames that are driven, and pixels emit light, within a unit of time based on both the average the grey level of each frame data and the difference in the average gray level between the data of adjacent two frames during the low-speed driving mode, thereby reducing a driving frequency of the pixel matrix to reduce power consumption of the display panel.

8. The apparatus of claim 7, wherein:

a driving frame period of the low-speed driving mode includes two or three successive frames arranged in a time interval of one frame period; and

a frame period between two driving frame periods is a hold frame period during which pixels hold a previous data voltage.