GOA circuit and driving method thereof, and touch display apparatus
First Claim
1. A GOA circuit, comprising a plurality of cascaded GOA units, wherein each GOA unit includes a first input terminal, a second input terminal, an output terminal, voltage terminals and a clock signal terminal;
- and the GOA circuit is configured to receive N clock signals in one clock period, the clock signal terminal of the GOA unit is configured to receive one of the N clock signals in one clock period, and N is a positive even number;
first input terminals of a first-level GOA unit to a (N/2)th-level GOA unit are coupled to a first signal terminal, a first input terminal of a (N/2+1)th-level GOA unit is coupled to an output terminal of the first-level GOA unit, a first input terminal of a (N/2+2)th-level GOA unit is coupled to an output terminal of a second-level GOA unit, and so on;
second input terminals of a last-level GOA unit to a (N/2)th last-level GOA unit are coupled to a second signal terminal, a second input terminal of a (N/2+1)th last-level GOA unit is coupled to an output terminal of the last-level GOA unit, a second input terminal of a (N/2+2)th last-level GOA unit is coupled to an output terminal of a second last-level GOA unit, and so on; and
N/2 cascaded GOA units of the plurality of cascaded GOA units are included in a pull-up node potential holding unit, and output terminals of the GOA units in the pull-up node potential holding unit are not coupled to gate lines.
1 Assignment
0 Petitions
Accused Products
Abstract
A GOA circuit includes a plurality of GOA units. First input terminals of a first-level GOA unit to a (N/2)th-level GOA unit are coupled to a first signal terminal, and a first input terminal of any one of other GOA units is coupled to an output terminal of a (N/2)th-level GOA unit located in front of the any one of other GOA units. Second input terminals of a last-level GOA unit to a (N/2)th last-level GOA unit are coupled to a second signal terminal, and a second input terminal of any one of other GOA units is coupled to an output terminal of a (N/2)th-level GOA unit located behind the any one of other GOA units. N is the number of clock signals in one clock period. N/2 cascaded GOA units of the GOA circuit are included in a pull-up node potential holding unit, and output terminals of the N/2 cascaded GOA units are not coupled to gate lines.
4 Citations
14 Claims
-
1. A GOA circuit, comprising a plurality of cascaded GOA units, wherein each GOA unit includes a first input terminal, a second input terminal, an output terminal, voltage terminals and a clock signal terminal;
- and the GOA circuit is configured to receive N clock signals in one clock period, the clock signal terminal of the GOA unit is configured to receive one of the N clock signals in one clock period, and N is a positive even number;
first input terminals of a first-level GOA unit to a (N/2)th-level GOA unit are coupled to a first signal terminal, a first input terminal of a (N/2+1)th-level GOA unit is coupled to an output terminal of the first-level GOA unit, a first input terminal of a (N/2+2)th-level GOA unit is coupled to an output terminal of a second-level GOA unit, and so on; second input terminals of a last-level GOA unit to a (N/2)th last-level GOA unit are coupled to a second signal terminal, a second input terminal of a (N/2+1)th last-level GOA unit is coupled to an output terminal of the last-level GOA unit, a second input terminal of a (N/2+2)th last-level GOA unit is coupled to an output terminal of a second last-level GOA unit, and so on; and N/2 cascaded GOA units of the plurality of cascaded GOA units are included in a pull-up node potential holding unit, and output terminals of the GOA units in the pull-up node potential holding unit are not coupled to gate lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
- and the GOA circuit is configured to receive N clock signals in one clock period, the clock signal terminal of the GOA unit is configured to receive one of the N clock signals in one clock period, and N is a positive even number;
Specification