Sensing charge recycling circuitry

• US 10,614,876 B1
• Filed: 10/31/2018
• Issued: 04/07/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Scott E.
• Primary Examiner(s): Lam, David
• Application Number:
  US16/176,891
• Publication Number:
  US 20200135258A1
• Time in Patent Office: 524 Days
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory device include one or more sections of memory banks. Each of the one or more sections may include multiple sensing amplifiers and a digit line to supply voltages to the sensing amplifiers during a refresh of the respective section. The memory device may also include transmission circuitry configured to transmit excess charge remaining on a first digit line of a first section to a second digit line of a second section after a refresh of the first section and before a refresh of the second section.

Claims

1. A memory device, comprising:

a first section of memory banks comprising;

a first plurality of sensing amplifiers;

a first digit line configured to supply a first voltage to the first plurality of sensing amplifiers during a refresh of the first section;

a second section of memory banks comprising;

a second plurality of sensing amplifiers; and

a second digit line configured to supply the first voltage to the second plurality of sensing amplifiers during a refresh of the second section; and

transmission circuitry configured to transmit excess charge remaining on the first digit line to the second digit line after the refresh of the first section and before the refresh of the second section, wherein the transmission circuitry comprises a plurality of parallel connections that selectively couple together the first section to the second section to transmit a plurality of excess charges in parallel.

2. The memory device of claim 1, wherein the first section of memory banks comprises a supply configured to be selectively driven by an array voltage supply and is configured to power the first digit line during the refresh of the first section and to be undriven by the array voltage supply when the excess charge is transmitted to the second digit line.

3. The memory device of claim 1, wherein the second section of the memory banks comprises a supply configured to be selectively driven by an array voltage supply and is configured to power the second digit line using the array voltage supply during a first portion of the refresh of the second section.

4. The memory device of claim 3, wherein the supply is configured to drive the second digit line using the excess charge during a second portion of the refresh of the second portion.

5. The memory device of claim 1, wherein the first and second sections are adjacent sections in a memory bank of the memory banks.

6. The memory device of claim 1, wherein the first and second sections are not adjacent sections in a memory bank of the memory banks.

7. The memory device of claim 1, wherein,

the first section comprises:

a third plurality of sensing amplifiers;

a third digit line configured to supply a second voltage to the third plurality of sensing amplifiers during the refresh of the first section; and

the second section of memory banks comprising;

a fourth plurality of sensing amplifiers; and

a fourth digit line configured to supply the second voltage to the fourth plurality of sensing amplifiers during the refresh of the second section.

8. The memory device of claim 7, wherein the transmission circuitry is configured to transmit charge between the third digit line and the fourth digit line after the refresh of the first section and before the refresh of the second section.

9. The memory device of claim 8, wherein the second voltage comprises VSS, and the first section of memory banks comprises a supply configured to be selectively driven by a VSS supply and is configured to drive the third digit line to VSS during the refresh of the first section and to be undriven by the VSS supply when the excess charge is transmitted between the third and fourth digit lines.

10. The memory device of claim 8, wherein the second voltage comprises VSS, and the second section of the memory banks comprises a supply configured to be selectively driven by a VSS supply and is configured to drive the fourth digit line using the VSS supply during a first portion of the refresh of the second section.

11. The memory device of claim 10, wherein the supply is configured to drive the fourth digit line using the transmitted charge between the third and fourth digit lines during a second portion of the refresh of the second portion.

12. A method comprising

refreshing a first portion of memory banks via a first digit line;

transmitting an amount of a remaining charge from the first digit line of the first portion to a second digit line of a second portion of the memory banks, wherein the remaining charge remains on the first digit line after refreshing the first portion;

refreshing the second portion of the memory banks based at least in part on the amount of the remaining charge;

transmitting a second amount of a second remaining charge from the second digit line of the second portion to a third digit line of a third portion of the memory banks, wherein the remaining charge remains on the second digit line after refreshing the second portion; and

refreshing the third portion of the memory banks based at least in part on the second amount of the second remaining charge.

13. The method of claim 12, wherein transmitting the amount of the remaining charge comprises shorting the first digit line to the second digit line.

14. The method of claim 13, wherein shorting the first digit line to the second digit line comprises shorting the first digit line to the second digit line via first and second local supplies of the respective first and second portions.

15. The method of claim 14, wherein refreshing the first portion comprises driving first local supply using an additional supply.

16. The method of claim 15, wherein transmitting the amount of the remaining charge comprises decoupling the first local supply from the additional supply.

17. The method of claim 12, comprising equalizing the first digit line with a third digit line of the first portion after the amount of the remaining charge has been transmitted from the first digit line and the second digit line.

18. A memory device, comprising:

a first digit line configured to supply a first voltage to a first plurality of sensing amplifiers during a refresh of a first section of memory banks of the memory device;

a second digit line configured to supply the first voltage to a second plurality of sensing amplifiers during a refresh of a second section of the memory banks;

a transistor configured to selectively couple the first digit line and the second digit line together to transmit excess charge remaining on the first digit line to the second digit line after the refresh of the first section and before the refresh of the second section;

a third digit line configured to supply a second voltage to a third plurality of sensing amplifiers during a refresh of the second section of the memory banks; and

an equalizer transistor configured to selectively couple the first and second digit lines together to equalize voltages of the first and third digit lines after the refresh of the first section.