Extended write modes for non-volatile static random access memory architectures having word level switches

• US 10,614,879 B2
• Filed: 07/24/2018
• Issued: 04/07/2020
• Est. Priority Date: 07/24/2018
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Tailliet, Francois, Battista, Marc
• Primary Examiner(s): Yoha, Connie C
• Application Number:
  US16/043,497
• Publication Number:
  US 20200035293A1
• Time in Patent Office: 623 Days
• Field of Search: 36523003, 36523005, 365154, 365189011
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of a) receiving a non-volatile write instruction including at least one address and at least one data word to be written to that at least one address, b) writing the at least one data word to the volatile memory cells of a word at the at least one address, and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

Claims

1. A method of performing a non-volatile write to a memory containing a plurality of non-volatile static random access memory (NVSRAM) cells grouped into words and addressable on a word-by-word basis, with each NVSRAM memory cell including a volatile memory cell and at least one non-volatile memory cell associated therewith, the method comprising steps of:

a) receiving a non-volatile write instruction, the non-volatile write instruction including at least one address and at least one data word to be written to the NVSRAM cells at that at least one address;

in response to receipt of the non-volatile write instruction;

b) writing the at least one data word to the volatile memory cells of the NVSRAM cells at the at least one address included within the non-volatile write instruction; and

c) at specified time, writing the at least one data word from the volatile memory cells of the NVSRAM cells at the least one address written to during step b) to the non-volatile memory cells associated to those volatile memory cells, but not writing data from other volatile memory cells of other NVSRAM cells to their associated non-volatile memory cells because those NVSRAM cells are not at the at least one address included within the non-volatile write instruction.

2. The method of claim 1, wherein the specified time is when chip deselection of the memory occurs.

3. The method of claim 1, wherein the at least one address comprises a starting address;

wherein the at least one data word comprises a plurality of data words; and

wherein step b) includes;

b1) writing a first data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of the word at the starting address;

b2) incrementing the starting address to produce a next address;

b3) writing a next data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of the word at the next address;

b4) if the plurality of data words contains another data word that was not yet written, increment the next address and returning to step b3); and

b5) if the plurality of data words does not contain another data word that was not yet written, proceeding to step c).

4. The method of claim 3, wherein the specified time is when chip deselection of the memory occurs.

5. The method of claim 3, wherein the specified time is not when chip deselection of the memory occurs.

6. The method of claim 1, wherein the at least one address comprises a plurality of addresses;

wherein the at least one data word comprises a plurality of data words; and

wherein step b) includes;

b1) writing a first data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of a word at a first of the plurality of addresses;

b2) writing a next data word of the plurality of data words to the volatile memory cells of a word of the NVSRAM cells of at a next of the plurality of addresses;

b3) if the next of the plurality of addresses is a last address of the plurality of addresses, proceeding to step c); and

b4) if the next of the plurality of addresses is not a last address of the plurality of addresses, returning to step b2).

7. The method of claim 6, wherein the specified time is when chip deselection of the memory occurs.

8. The method of claim 6, wherein the specified time is not when chip deselection of the memory occurs.

9. An electronic device, comprising:

a memory array comprising a plurality of non-volatile static random access memory (NVSRAM) cells grouped into words and addressable on a word-by-word basis, with each NVSRAM memory cell including a volatile memory cell and at least one non-volatile memory cell associated therewith;

a plurality of word level switches, each word level switch being associated with one word and permitting writing of data to the non-volatile memory cells of the NVSRAM cells of that word;

control circuitry configured to perform steps of;

a) receiving a non-volatile write instruction, the non-volatile write instruction including at least one address and at least one data word to be written to the NVSRAM cells at that at least one address;

in response to receipt of the non-volatile write instruction;

b) writing the at least one data word to the volatile memory cells of the NVSRAM cells a word at the at least one address included within the non-volatile write instruction; and

c) at specified time, writing the at least one data word from the volatile memory cells of the NVSRAM cells at the at least one address written to during step b) to the non-volatile memory cells associated to those volatile memory cells, but not writing data from other volatile memory cells of other NVSRAM cells to their associated non-volatile memory cells because those NVSRANM cells are not at the at least one address included within the non-volatile write instruction.

10. The electronic device of claim 9, wherein the specified time is when chip deselection of the memory array occurs.

11. The electronic device of claim 9, wherein the specified time is not when chip deselection of the memory array occurs.

12. The electronic device of claim 9, wherein the at least one address comprises a plurality of addresses;

wherein the at least one data word comprises a plurality of data words; and

wherein step b) includes;

b1) writing a first data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of a word at a first of the plurality of addresses;

b2) writing a next data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of a word at a next of the plurality of addresses;

b3) if the next of the plurality of addresses is a last address of the plurality of addresses, proceeding to step c); and

b4) if the next of the plurality of addresses is not a last address of the plurality of addresses, returning to step b2).

13. The electronic device of claim 12, wherein the specified time is when chip deselection of the memory array occurs.

14. The electronic device of claim 12, wherein the specified time is not when chip deselection of the memory array occurs.

15. A method of operating a non-volatile static random access memory (NVSRAM) addressable on a word-by-word basis, comprising:

a) receiving a non-volatile write instruction, the non-volatile write instruction including at least one address and at least one data word to be written to NVSRAM cells at that at least one address;

b) writing the at least one data word to volatile memory cells of the NVSRAM cells of a word at the at least one address; and

c) writing data from the volatile memory cells of the NVSRAM cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing but not writing data from other volatile memory cells of other NVSRAM cells to their associated non-volatile memory cells because those NVSRAM cells are not at the at least one address included within the non-volatile write instruction.

16. The method of claim 15, wherein the at least one address comprises a starting address;

wherein the at least one data word comprises a plurality of data words; and

wherein step b) includes;

b1) writing a first data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of the word at the starting address;

b2) incrementing the starting address to produce a next address;

b3) writing a next data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of the word at the next address;

b4) if the plurality of data words contains another data word that was not yet written, increment the next address and returning to step b3); and

b5) if the plurality of data words does not contain another data word that was not yet written, proceeding to step c).

17. The method of claim 15, wherein the at least one address comprises a plurality of addresses;

wherein the at least one data word comprises a plurality of data words; and

wherein step b) includes;

b1) writing a first data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of a word at a first of the plurality of addresses;

b2) writing a next data word of the plurality of data words to the volatile memory cells of the NVSRAM cells of a word at a next of the plurality of addresses;

b3) if the next of the plurality of addresses is a last address of the plurality of addresses, proceeding to step c); and

b4) if the next of the plurality of addresses is not a last address of the plurality of addresses, returning to step b2).