Memory system that selectively writes in single-level cell mode or multi-level cell mode to reduce program/erase cycles

• US 10,614,888 B2
• Filed: 01/22/2018
• Issued: 04/07/2020
• Est. Priority Date: 01/25/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Igahara, Shunichi, Hida, Toshikatsu
• Primary Examiner(s): Matin, Tasnima
• Application Number:
  US15/876,923
• Publication Number:
  US 20180211708A1
• Time in Patent Office: 806 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2207/2209 Concurrent read and write for multi-port memory G11C7/1075
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.

Claims

1. A memory system capable of being connected to a host, the system comprising:

a non-volatile memory having a plurality of memory cells; and

a controller that is electrically connected to the non-volatile memory, and is configured to carry out write operations, in response to write commands received from the host, in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n, wherein the controller is further configured to

determine whether an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more,

upon determining that the idle time has not continued for the threshold period of time or more, carry out a write operation to write data items into the non-volatile memory in the second mode in response to a write command received from the host,

upon determining that the idle time has continued for the threshold period of time or more;

increase the allowable data amount by a first data amount, and

after the increase, carry out a write operation to write data items into the non-volatile memory in the first mode in response to a write command received from the host.

2. The memory system according to claim 1, wherein the controller is configured to carry out write operations, after the increase and in response to write commands received from the host, to write data items in the non-volatile memory in the first mode until the first data amount of data items has been written, and then, to write data items into the non-volatile memory in the second mode.

3. The memory system according to claim 1,

wherein the controller is configured to determine the number of free blocks in the non-volatile memory and increase the allowable data amount by the first data amount upon determining that the number of free blocks is equal to or greater than a first threshold.

4. The memory system according to claim 1,

wherein the controller is configured to compare the allowable data amount against a maximum amount of data items capable of being written in the first mode, and increase the allowable data amount by the first data amount upon determining that the allowable data amount is less than the maximum amount.

5. The memory system according to claim 1,

wherein the controller is configured to determine a total number of program/erase cycles for all blocks of the non-volatile memory, and increase the allowable data amount by the first data amount upon determining that the total number is equal to or less than a second threshold.

6. The memory system according to claim 5,

wherein the controller is configured to allocate a free block of which the number of program/erase cycles is equal to or less than a third threshold, as a writing destination block in which data items are to be written in the first mode, when the total number of program/erase cycles for all blocks is equal to or less than the second threshold.

7. The memory system according to claim 1,

wherein the controller is configured to determine a maximum number of program/erase cycles in all blocks of the non-volatile memory, and increase the allowable data amount by the first data amount upon determining that the maximum number is equal to or less than a fourth threshold.

8. The memory system according to claim 1,

wherein the controller is configured to determine an average number of program/erase cycles of all blocks of the non-volatile memory, and increase the allowable data amount by the first data amount upon determining that the average number is equal to or less than a fifth threshold.

9. The memory system according to claim 1,

wherein the controller is configured to determine a minimum number of program/erase cycles in all blocks of the non-volatile memory, and increase the allowable data amount by the first data amount upon determining that the minimum number is equal to or less than a sixth threshold.

10. The memory system according to claim 1,

wherein the command used in determining that the idle state is a write command from the host.

11. The memory system according to claim 1,

wherein the command used in determining that the idle state is an I/O command from the host.

12. The memory system according to claim 1,

wherein the command used in determining that the idle state is either an I/O command or a control command from the host.

13. The memory system according to claim 1,

wherein the controller is configured to further determining that the idle state has continued when a power management command for requesting transition to a low power state is received from the host.

14. A control method for a non-volatile memory having a plurality of memory cells, said method comprising:

carrying out a write operation, in response to write commands received from a host, in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, carrying out write operations in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n;

determining whether an idle state, in which a command has not been received from a host, has continued for a threshold period of time or more;

upon determining that the idle time has not continued for the threshold period of time or more, carry out a write operation to write data items into the non-volatile memory in the second mode in response to a write command received from the host,

upon determining that the idle time has continued for the threshold period of time or more;

increasing the allowable data amount by a first data amount; and

after the increase, carrying out a write operation to write data items into the non-volatile memory in the first mode in response to a write command received from the host.

15. The control method according to claim 14, further comprising:

after the increase and in response to write commands received from the host, carrying out write operations to write data items into the non-volatile memory in the first mode until the first data amount of data items has been written, and then, to write data items in the non-volatile memory in the second mode.

16. The control method according to claim 15, further comprising:

determining the number of free blocks in the non-volatile memory,

wherein the allowable data amount is increased by the first data amount upon determining that the number of free blocks is equal to or greater than a first threshold.

17. The control method according to claim 15, further comprising:

comparing the allowable data amount against a maximum amount of data items capable of being written in the first mode,

wherein the allowable data amount is increased by the first data amount upon determining that the allowable data amount is less than the maximum amount.

18. A computer system comprising:

a host; and

a storage device in communication with the host, the storage device including a non-volatile memory having a plurality of memory cells and a controller that is electrically connected to the non-volatile memory and configured to carry out write operations, in response to write commands received from the host, in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n,

wherein the controller is further configured to determine whether an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, carry out a write operation to write data items into the nonvolatile memory in the second mode in response to the write command received from the host in response to determining that the idle time has not continued for the threshold period of time or more, increase the allowable data amount by a first data amount in response to determining that the idle state has continued for the threshold period of time or more, and after the increase and in response to determining that the idle state has continued for the threshold period of time or more, carry out a write operation to write data items into the non-volatile memory in the first mode in response to a write command received from the host.

19. The computer system according to claim 18, wherein the controller is configured to carry out write operations, after the increase and in response to write commands received from the host, to write data items into the non-volatile memory in the first mode until the first data amount of data items has been written, and then, to write data items in the non-volatile memory in the second mode.

20. The computer system according to claim 19,

wherein the command used in detecting the idle state is one of a read command from the host, a write command from the host, and a control command from the host.