Stack viabar structures

• US 10,615,027 B1
• Filed: 10/25/2018
• Issued: 04/07/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fan, Su Chen, Chen, Hsueh-Chung, Mignot, Yann, Kelly, James J., Hook, Terence B.
• Primary Examiner(s): Menz, Douglas M
• Application Number:
  US16/170,465
• Publication Number:
  US 20200135457A1
• Time in Patent Office: 530 Days
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76858 by diffusing alloying elements
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices

Abstract

Various methods and structures for fabricating a semiconductor structure. The semiconductor structure includes in a top layer of a semiconductor stack a semiconductor contact located according to a first horizontal pitch. A first metallization layer is disposed directly on the top layer and includes a metallization contact located according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that the location of the metallization contact is vertically mismatched from the location of the semiconductor contact. A second metallization layer is disposed directly on the first metallization layer. The second metallization layer includes a super viabar structure that forms an electrical interconnect, in the second metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first metallization layer.

Claims

1. A semiconductor structure comprising:

a semiconductor stack disposed on a substrate, a top layer of the semiconductor stack including at least one semiconductor contact located in the top layer of the semiconductor stack according to a first horizontal pitch;

a first BEOL metallization layer disposed directly on the top layer of the semiconductor stack, the first BEOL metallization layer including at least one metallization contact located in the first BEOL metallization layer according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that a location of the at least one metallization contact is vertically mismatched from the location of the at least one semiconductor contact; and

a second BEOL metallization layer disposed directly on the first BEOL metallization layer, the second BEOL metallization layer including a super viabar structure that forms an electrical interconnect, in the second BEOL metallization layer, between the at least one semiconductor contact and the at least one metallization contact.

2. The semiconductor structure of claim 1, wherein the semiconductor stack disposed on the substrate includes a plurality of electronic devices in a circuit disposed on the circuit supporting substrate, a first electronic device in the plurality of electronic devices comprising a first field-effect transistor (FET) and a second electronic device in the plurality of electronic devices comprising a second FET, the super viabar structure providing an electrical interconnect, in the second BEOL metallization layer, between the first FET and the second FET.

3. The semiconductor structure of claim 1, wherein the super viabar structure in the second BEOL metallization layer providing a modular add-on electrical interconnect on top of the first BEOL metallization layer, for interconnecting the vertically mismatched at least one metallization contact in the first BEOL metallization layer with the at least one semiconductor contact in the top layer of the semiconductor stack.

4. The semiconductor structure of claim 1, further comprising:

a metal cap disposed directly on the at least one metallization contact located in the first BEOL metallization layer, the metal cap being interposed between the at least one metallization contact in the first BEOL metallization layer and the electrical interconnect of the super viabar structure in the second BEOL metallization layer.

5. The semiconductor structure of claim 4, wherein the metal cap is made of a metal alloy.

6. The semiconductor structure of claim 1, wherein the at least one semiconductor contact comprises Tungsten, the at least one metallization contact located in the first BEOL metallization layer comprises Copper, and the super viabar structure in the second BEOL metallization layer comprises Copper.

7. The semiconductor structure of claim 1, wherein the at least one semiconductor contact comprises Cobalt, the at least one metallization contact located in the first BEOL metallization layer comprises Copper, and the super viabar structure in the second BEOL metallization layer comprises Copper.

8. The semiconductor structure of claim 1, wherein the at least one semiconductor contact comprises Cobalt, the at least one metallization contact located in the first BEOL metallization layer comprises Cobalt, and the super viabar structure in the second BEOL metallization layer comprises Cobalt.

9. The semiconductor structure of claim 1, wherein the at least one semiconductor contact comprises Cobalt, the at least one metallization contact located in the first BEOL metallization layer comprises Ruthenium, and the super viabar structure in the second BEOL metallization layer comprises Ruthenium.

10. The semiconductor structure of claim 1, wherein the at least one semiconductor contact comprises Ruthenium, the at least one metallization contact located in the first BEOL metallization layer comprises Cobalt, and the super viabar structure in the second BEOL metallization layer comprises Cobalt.

11. A method for fabricating an electrical contact in a BEOL metallization layer for a semiconductor structure, the method comprising:

providing a semiconductor stack disposed on a circuit supporting substrate;

patterning a top layer of the semiconductor stack to provide at least one semiconductor contact located in the top layer of the semiconductor stack according to a first horizontal pitch;

patterning a first BEOL metallization layer disposed directly on the top layer of the semiconductor stack, to provide at least one metallization contact located in the first BEOL metallization layer according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that a location of the at least one metallization contact is vertically mismatched from the location of the at least one semiconductor contact; and

patterning a second BEOL metallization layer disposed directly on the first BEOL metallization layer, followed by deposition of a metal fill material filling a via trench in the first BEOL metallization layer and the second BEOL metallization layer, to provide a super viabar structure that forms an electrical interconnect, in the second BEOL metallization layer, between the at least one semiconductor contact in the top layer of the semiconductor stack and the at least one metallization contact in the first BEOL metallization layer.

12. The method of claim 11, wherein the super viabar structure in the second BEOL metallization layer is a modular add-on electrical interconnect on top of the first BEOL metallization layer, for interconnecting the vertically mismatched at least one metallization contact in the first BEOL metallization layer with the at least one semiconductor contact in the top layer of the semiconductor stack.

13. The method of claim 11, further comprising:

perform via patterning in the second BEOL metallization layer to expose in a via trench a top surface of the at least one metallization contact in the first BEOL metallization layer;

perform selective deposition of conductive material on the exposed top surface of the at least one metallization contact to form a metal cap on the exposed top surface of the at least one metallization contact;

perform trench etch in the via trench and in the first BEOL metallization layer to expose in the via trench a top surface of the at least one semiconductor contact in the top layer of the semiconductor stack; and

perform deposition of a metal fill material filling the via trench in the first BEOL metallization layer and the second BEOL metallization layer, to form the super via bar structure providing the electrical interconnect, in the second BEOL metallization layer, between the at least one semiconductor contact in the top layer of the semiconductor stack and the at least one metallization contact in the first BEOL metallization layer.

14. The method of claim 13, further comprising:

perform, before the deposition of the metal fill material filling the via trench in the first BEOL metallization layer and the second BEOL metallization layer, removal of the metal cap to expose in the via trench the top surface of the at least one metallization contact in the first BEOL metallization layer.

15. The method of claim 13, wherein the metal cap being disposed directly on the at least one metallization contact located in the first BEOL metallization layer, and the metal cap being interposed between the at least one metallization contact and the electrical interconnect of the super viabar structure in the second BEOL metallization layer.

16. The method of claim 13, wherein the metal cap is made of a metal alloy.

17. The method of claim 13, further comprising:

thermally treating the metal cap, disposed on the top surface of the at least one metallization contact in the first BEOL metallization layer, to form a metal alloy in the metal cap.

18. The method of claim 13, wherein the at least one semiconductor contact comprises at least one metal selected from the following set:

Tungsten, Cobalt, and Ruthenium; and

wherein the at least one metallization contact located in the first BEOL metallization layer comprises Cobalt, and the super viabar structure in the second BEOL metallization layer comprises Cobalt.

19. The method of claim 13, wherein the at least one semiconductor contact comprises at least one metal selected from the following set:

Tungsten, Cobalt, and Ruthenium; and

wherein the at least one metallization contact located in the first BEOL metallization layer comprises Copper, and the super viabar structure in the second BEOL metallization layer comprises Copper.

20. The method of claim 13, wherein the at least one semiconductor contact comprises at least one metal selected from the following set:

Tungsten, Cobalt, and Ruthenium; and

wherein the at least one metallization contact located in the first BEOL metallization layer comprises Ruthenium, and the super viabar structure in the second BEOL metallization layer comprises Ruthenium.