Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device

• US 10,615,043 B2
• Filed: 04/11/2018
• Issued: 04/07/2020
• Est. Priority Date: 09/12/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ando, Takashi, Hashemi, Pouya, Jagannathan, Hemanth, Lee, Choonghyun, Narayanan, Vijay
• Primary Examiner(s): Hossain, Moazzam
• Application Number:
  US15/951,149
• Publication Number:
  US 20180233370A1
• Time in Patent Office: 727 Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02326 into a nitride layer, e.g. changing SiN to SiON
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a dummy gate structure on a silicon-germanium (SiGe) channel layer of a FET (field effect transistor) device, wherein forming the dummy gate structure comprises;

growing a dummy silicon oxide layer on a surface of the SiGe channel layer using a first oxynitridation process, wherein the dummy silicon oxide layer comprises nitrogen; and

forming a dummy gate electrode layer over the dummy silicon oxide layer; and

performing a RMG (replacement metal gate) process which comprises removing the dummy gate structure from the SiGe channel layer, and forming a metal gate structure on the SiGe channel layer, wherein forming the metal gate structure on the SiGe channel layer comprises;

growing an interfacial silicon oxide layer on the surface of SiGe channel layer using a second oxynitridation process, wherein the interfacial silicon oxide layer is substantially devoid of germanium oxide and nitrogen;

wherein the first oxynitridation process is configured to chemically treat the surface of the SiGe channel layer in a way which prevents formation of germanium oxide, and which prevents the incorporation of nitrogen within the interfacial silicon oxide layer, during growth of the interfacial silicon oxide layer;

forming a high-k dielectric layer on the interfacial silicon oxide layer, wherein k is greater than 4; and

forming a metal gate electrode layer on the high-k dielectric layer.

2. The method of claim 1, wherein growing the dummy silicon oxide layer on the surface of the SiGe channel layer comprises growing a silicon oxynitride (SiON) layer on the SiGe channel layer.

3. The method of claim 1, wherein growing an interfacial silicon oxide layer on the surface of the SiGe channel layer comprises growing a silicon dioxide layer on the surface of the SiGe channel layer.

4. The method of claim 1, wherein the first oxynitridation process is performed by a process comprising:

performing a first rapid thermal anneal process in a gas mixture atmosphere comprising ammonia (NH₃) at a first temperature; and

performing a second rapid thermal anneal process in a gas mixture atmosphere comprising oxygen (O₂) at a second temperature.

5. The method of claim 4, wherein the second oxynitridation process is the same as the first oxynitridation process.

6. The method of claim 1, wherein the SiGe channel layer comprises a Ge content in a range of about 20% to about 70%.

7. The method of claim 1, wherein forming the dummy gate structure further comprises depositing a silicon oxide layer on the dummy silicon oxide layer before forming the dummy gate electrode layer.

8. The method of claim 1, wherein forming the metal gate structure further comprises forming a conformal work function metal layer on the high-k dielectric layer prior to forming the metal gate electrode layer.

9. The method of claim 1, wherein the FET device comprises a planar FET device.

10. The method of claim 1, wherein the FET device comprises a three-dimensional FET device.

11. The method of claim 10, wherein the three-dimensional FET device comprises a FinFET device.