Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 10,615,163 B2
• Filed: 09/17/2019
• Issued: 04/07/2020
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/573,302
• Publication Number:
  US 20200013780A1
• Time in Patent Office: 203 Days
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. A semiconductor memory array comprising:

a plurality of links or strings of semiconductor memory cells, wherein each of said semiconductor memory cells includes;

a floating body region configured to store data as charge therein to define a state of said memory cell selected from at least first and second states, wherein current flow through said memory cell is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of said memory cell;

wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.

2. The semiconductor memory array of claim 1, wherein each of said semiconductor memory cells comprises first and second conductive regions interfacing with said floating body region.

3. The semiconductor memory array of claim 2, wherein each of said semiconductor memory cells further comprises a gate region positioned between said first and second conductive regions.

4. The semiconductor memory array of claim 2, wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types, said first conductive region, said second conductive region, and said back-bias region have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

5. The semiconductor memory array of claim 4, further comprising a substrate having said first conductivity type.

6. The semiconductor memory array of claim 1, wherein when a state of a first memory cell of said semiconductor memory cells is in one of said first and second states and a state of a second memory cell of said semiconductor memory cells is in one of said first and second states, application of voltage to said back-bias region maintains said first and second memory cells in said states.

7. The semiconductor memory array of claim 6, wherein said state of said first memory cell is different from said state of said second memory cell.

8. An integrated circuit comprising:

a plurality of links or strings of semiconductor memory cells, wherein each of said semiconductor memory cells includes;

a floating body region configured to store data as charge therein;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region;

wherein said back-bias region is configured to establish at least two different stable floating body charge levels by application of voltage to said back-bias region;

wherein current flow through said memory cell is larger when said memory cell is in one of at least two different stable floating body charge levels than when said memory cell is in another of said at least two different stable floating body charge levels;

wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells; and

a control circuitry configured to apply said voltage to said back-bias region.

9. The integrated circuit of claim 8, wherein said voltage applied to said back-bias region is a constant positive voltage bias.

10. The integrated circuit of claim 8, wherein said voltage applied to said back-bias region is a periodic pulse of positive voltage.

11. The integrated circuit of claim 8, wherein when a first memory cell of said semiconductor memory cells is in one of said at least two different stable floating body charge levels and a second memory cell of said semiconductor memory cells is in one of said at least two different stable floating body charge levels, applications of voltage to said back-bias regions maintain said first and second memory cells at said stable floating body charge levels.

12. The integrated circuit of claim 11, wherein said first memory cell is at a first stable floating body charge level and said second memory cell is at a second stable floating body charge level and said first stable floating body charge level is different from said second stable floating body charge level.

13. The integrated circuit of claim 8, wherein each said floating body region has a first conductivity type selected from p-type and n-type conductivity types, each said first region, second region, and back-bias region have a second conductivity type selected from p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

14. The integrated circuit of claim 8, further comprising a substrate having a first conductivity type selected from p-type and n-type conductivity types.

15. The integrated circuit of claim 8, wherein application of voltage to said back-bias regions maintains current states of each said memory cell connected thereto.

16. An integrated circuit comprising:

a plurality of links or strings of semiconductor memory cells, wherein each of said semiconductor memory cells includes;

a floating body region configured to store data as charge therein to define a state of said memory cell selected from at least first and second states, wherein current flow through said memory cell is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; and

a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of said memory cell;

wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells; and

a control circuitry configured to apply said voltage to said back-bias region.

17. The integrated circuit of claim 16, wherein each of said semiconductor memory cells comprises first and second conductive regions interfacing with said floating body region.

18. The integrated circuit of claim 17, wherein each of said semiconductor memory cells further comprises a gate region positioned between said first and second conductive regions.

19. The integrated circuit of claim 17, wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types, said first conductive region, said second conductive region, and said back-bias region have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

20. The integrated circuit of claim 19, further comprising a substrate having said first conductivity type.

21. The integrated circuit of claim 16, wherein when a first memory cell of said semiconductor memory cells is in one of said at least first and second states and a second memory cell of said semiconductor memory cells is in one of said at least first and second states, applications of voltage to said back-bias regions maintain said first and second memory cells in said states.

22. The integrated circuit of claim 21, wherein said state of said first memory cell is different from said state of said second memory cell.