Ferro-electric complementary FET

• US 10,615,176 B2
• Filed: 11/22/2017
• Issued: 04/07/2020
• Est. Priority Date: 11/22/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Frank, David J., Solomon, Paul M., Sun, Xiao
• Primary Examiner(s): Muse, Ismail A
• Application Number:
  US15/821,425
• Publication Number:
  US 20190157278A1
• Time in Patent Office: 867 Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 51/30 characterised by the memory core region

Abstract

A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

Claims

1. A 2-NAND gate, comprising:

a first field-effect transistor (FET) and a second FET, wherein each FET comprises;

a semiconductor substrate having a first side, a second side opposite from the first side, a third side that connects the first side and the second side, and a fourth side opposite the third side that connects the first side and the second side; and

a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises

a gate insulating layer; and

a ferroelectric material layer disposed on the gate insulating layer,

wherein a portion of the upper surface of the substrate that extends from the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first side and the second side, and

a portion of the upper surface of the substrate that extends from the third side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the fourth side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the third side and the fourth side; and

a self-aligned silicided short between a first n-type contact along the first side of the second FET and a first p-type contact along the third side of the second FET,

wherein

a second n-type contact along the second side of the first FET is connected to ground,

a second p-type contact along the fourth side of the first FET and a second p-type contact along the fourth side of the second FET are connected to a supply voltage,

a second n-type contact along the second side of the second is connected to a first n-type contact along the first side of the first FET, and

a first p-type, contact along the third side of the first FET and the self-aligned shielded short are connected to an output terminal.

2. A parasitic p-field-effect transistor (FET), comprising:

a semiconductor substrate having a first side, a second side opposite from the first side, a third side that connects the first side and the second side, and a fourth side opposite the third side that connects the first side and the second side; and

a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises

a gate insulating layer; and

a ferroelectric material layer disposed on the gate insulating layer,

wherein a portion of the upper surface of the substrate that extends from the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first side and the second side,

a portion of the upper surface of the substrate that extends from the third side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from the fourth side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the third side and the fourth side,

a first n-type contact along the first side is connected to an input terminal,

a first p-type contact along the third side is connected to a supply voltage,

a second n-type contact along the second side is connected to an output terminal, and

a second p-type contact along the fourth side is unconnected, and

wherein a presence of both and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

3. An SRAM circuit, comprising:

first, second, third and fourth parasitic field-effect transistors (FETs) as recited in claim 2;

a first via that connects an output of a first FET to an input of a second FET;

a third via that connects an output of the second FET to an input of a third FET;

a second via that connects an output of the third FET to an input of the fourth p-FET;

a fourth via that connects an output of the second HT to an input of the fourth FET, wherein

an input of the first FET is connected to a left bit line,

an output of the fourth FET is connected to a right bit line,

the ferroelectric gate stacks of the first and fourth FETs are connected to word lines, and

second p-type contacts of the second and third FETS are connected to ground.

4. A field-effect transistor (FET), comprising:

a semiconductor substrate having a first side and a second side opposite from the first side; and

a ferroelectric gate stack disposed on a central portion of an upper surface of the substrate, wherein the ferroelectric gate stack comprises

a gate insulating layer; and

a ferroelectric material layer disposed on the gate insulating layer,

wherein a portion of the upper surface of the substrate that extends from a first portion of the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from a first portion of the second side to under the ferroelectric gate stack is doped with n-type impurities forming n-type contacts along the first portion of the first side and the first portion of the second side, and

a portion of the upper surface of the substrate that extends from a second portion of the first side that is adjacent to the first portion of the first side to under the ferroelectric gate stack and a portion of the upper surface of the substrate that extends from a second portion of the second side that is adjacent to the first portion of the second side to under the ferroelectric gate stack is doped with p-type impurities forming p-type contacts along the second portion of the first side and the second portion of the second side,

wherein a presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

5. The FET of claim 4, further comprising a metal layer disposed on the ferroelectric material layer.

6. The FET of claim 4, further comprising a silicide Hock out mask between the p-type contact on the second portion of the first side from the n-type contact on the first portion of the first side that separates the p-type contact on the second portion of the first side from the n-type contact on the first portion of the first side.

7. The FET of claim 6, further comprising a silicide block out mask between the second portion of the second side from the n-type contact on the first portion of the second side that separates the p-type contact on the second portion of the second side from the n-type contact on the first portion of the second side.

8. The FET claim 4, wherein the ferroelectric gate stack has a width to length (WI) ratio that is not equal to 1.