Semiconductor device and method for manufacturing the same

• US 10,615,179 B2
• Filed: 03/19/2018
• Issued: 04/07/2020
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US15/925,096
• Publication Number:
  US 20180211980A1
• Time in Patent Office: 750 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Claims

1. A semiconductor device comprising:

a first conductive layer;

a first insulating layer over the first conductive layer;

a semiconductor layer over the first insulating layer;

a second insulating layer over the semiconductor layer; and

a second conductive layer over the second insulating layer,

wherein a bottom surface of the second conductive layer is located lower than a channel formation region of the semiconductor layer in a channel width direction of the semiconductor layer, and

wherein the channel width direction matches a direction in which the semiconductor device is likely to be bent.

2. The semiconductor device according to claim 1, wherein the semiconductor layer is an oxide semiconductor layer comprising indium, gallium, and zinc.

3. The semiconductor device according to claim 1, wherein the second conductive layer is in contact with the first conductive layer.

4. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein a channel width of the semiconductor layer is larger that a channel length of the semiconductor layer.

6. A semiconductor device comprising:

a first conductive layer;

a first insulating layer over the first conductive layer;

a semiconductor layer over the first insulating layer;

a second insulating layer over the semiconductor layer; and

a second conductive layer over the second insulating layer,

wherein a bottom surface of the second conductive layer is located lower than a channel formation region of the semiconductor layer in a channel width direction of the semiconductor layer, and

wherein the channel width direction matches a direction in which the semiconductor device is frequently bent.

7. The semiconductor device according to claim 6, wherein the semiconductor layer is an oxide semiconductor layer comprising indium, gallium, and zinc.

8. The semiconductor device according to claim 6, wherein the second conductive layer is in contact with the first conductive layer.

9. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the oxide semiconductor layer.

10. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the oxide semiconductor layer.

11. The semiconductor device according to claim 6, wherein a channel width of the semiconductor layer is larger than a channel length of the semiconductor layer.

12. A semiconductor device comprising:

a first conductive layer;

a first insulating layer over the first conductive layer;

a semiconductor layer over the first insulating layer;

a second insulating layer over the semiconductor layer; and

a second conductive layer over the second insulating layer,

wherein a bottom surface of the second conductive layer is located lower than a channel formation region of the semiconductor layer in a channel width direction of the semiconductor layer, and

wherein the channel width direction matches a direction in which the semiconductor device is curved.

13. The semiconductor device according to claim 12, wherein the semiconductor layer is an oxide semiconductor layer comprising indium, gallium, and zinc.

14. The semiconductor device according to claim 12, wherein the second conductive layer is in contact with the first conductive layer.

15. The semiconductor device according to claim 12, wherein a channel width of the semiconductor layer is larger than a channel length of the semiconductor layer.

16. A semiconductor device comprising:

a gate electrode layer;

a semiconductor layer; and

an insulating layer between the gate electrode layer and the semiconductor layer,

wherein the gate electrode layer extends beyond a side edge of the semiconductor layer in a channel width direction of the semiconductor layer, and

wherein the channel width direction matches a direction in which the semiconductor device is likely to be bent.

17. The semiconductor device according to claim 16, wherein a channel width of the semiconductor layer is larger than a channel length of the semiconductor layer.

18. A semiconductor device comprising:

a gate electrode layer;

a semiconductor layer; and

an insulating layer between the gate electrode layer and the semiconductor layer,

wherein the gate electrode layer extends beyond a side edge of the semiconductor layer in a channel width direction of the semiconductor layer, and

wherein the channel width direction matches a direction in which the semiconductor device is frequently bent.

19. The semiconductor device according to claim 18, wherein a channel width of the semiconductor layer is larger than a channel length of the semiconductor layer.

20. A semiconductor device comprising:

a gate electrode layer;

a semiconductor layer; and

an insulating layer between the gate electrode layer and the semiconductor layer,

wherein the gate electrode layer extends beyond a side edge of the semiconductor layer in a channel width direction of the semiconductor layer, and

wherein the channel width direction matches a direction in which the semiconductor device is curved.

21. The semiconductor device according to claim 20, wherein a channel width of the semiconductor layer is larger than a channel length of the semiconductor layer.

22. A semiconductor device comprising:

a driver circuit portion comprising;

a gate electrode layer;

a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer;

an insulating layer between the gate electrode layer and each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;

a source electrode layer electrically connected to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; and

a drain electrode layer electrically connected to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer,

wherein the gate electrode layer extends beyond both side edges of the first semiconductor layer, both side edges of the second semiconductor layer, and both side edges of the third semiconductor layer in a channel width direction of each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer,

wherein the channel width direction of each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer matches a direction in which the semiconductor device is to be curved, and

wherein in each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, a channel width is larger than a channel length.

23. A semiconductor device comprising:

a driver circuit portion comprising;

a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer which are located between insulating layers;

a conductive layer over and in contact with a top surface of one of the insulating layers;

a source electrode layer electrically connected to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; and

a drain electrode layer electrically connected to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer,

wherein the conductive layer extends beyond both side edges of the first semiconductor layer, both side edges of the second semiconductor layer, and both side edges of the third semiconductor layer in a channel width direction of each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer,

wherein the channel width direction of each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer matches a direction in which the semiconductor device is to be curved, and

wherein in each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, a channel width is larger than a channel length.