Nanosheet transistor gate structure having reduced parasitic capacitance

• US 10,615,256 B2
• Filed: 06/27/2018
• Issued: 04/07/2020
• Est. Priority Date: 06/27/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Miao, Xin, Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US16/020,316
• Publication Number:
  US 20200006477A1
• Time in Patent Office: 650 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Embodiments are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device on a substrate. The fabrication operations include, forming a channel stack over the substrate, wherein the channel stack include stacked and spaced apart channel nanosheets. A metal gate is formed adjacent to end regions of the channel stack and around and between the stacked and spaced apart channel nanosheets. A permanent dummy gate is formed above the channel stack.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

performing fabrication operations to form a nanosheet field effect transistor device on a substrate, wherein the fabrication operations include;

forming a channel stack over the substrate, wherein the channel stack comprises stacked and spaced apart channel nanosheets;

forming a metal gate located adjacent to end regions of the channel stack and further located around and between the stacked and spaced apart channel nanosheets; and

forming a permanent dummy gate above the channel stack.

2. The method of claim 1 further comprising forming a source or a drain (S/D) region above the substrate and adjacent to the channel stack.

3. The method of claim 2 further comprising forming a S/D contact communicatively coupled to the S/D region.

4. The method of claim 3, wherein the S/D contact is adjacent to and spaced apart from the permanent dummy gate.

5. The method of claim 4, wherein a dielectric gate spacer is adjacent the permanent dummy gate.

6. The method of claim 5, wherein the dielectric gate spacer is between the permanent dummy gate and the S/D contact.

7. The method of claim 6, wherein the permanent dummy gate, the dielectric gate spacer and the S/D contact do not generate parasitic capacitance.

8. The method of claim 1 further comprising forming a gate contact communicatively coupled to the metal gate.

9. The method of claim 8, wherein the gate contact is adjacent to and spaced apart from the permanent dummy gate.

10. The method of claim 9, wherein a dielectric cap region is adjacent the permanent dummy gate.

11. The method of claim 10, wherein the dielectric cap region is between the permanent dummy gate and the gate contact.

12. The method of claim 11, wherein the permanent dummy gate, the dielectric cap region and the gate contact do not generate parasitic capacitance.

13. A nanosheet field effect transistor device comprising:

a channel stack formed over a substrate, wherein the channel stack comprises stacked and spaced apart channel nanosheets;

a metal gate located adjacent to end regions of the channel stack and further located around and between the stacked and spaced apart channel nanosheets; and

a permanent dummy gate formed above the channel stack.

14. The device of claim 13 further comprising forming a source or a drain (S/D) region above the substrate and adjacent to the channel stack.

15. The device of claim 14 further comprising a S/D contact communicatively coupled to the S/D region.

16. The device of claim 15, wherein the S/D contact is adjacent to and spaced apart from the permanent dummy gate.

17. The device of claim 16, wherein a dielectric gate spacer is adjacent the permanent dummy gate.

18. The device of claim 17, wherein the dielectric gate spacer is between the permanent dummy gate and the S/D contact.

19. The device of claim 18, wherein the permanent dummy gate, the dielectric gate spacer and the S/D contact do not generate parasitic capacitance.

20. The device of claim 19 further comprising:

forming a gate contact communicatively coupled to the metal gate;

wherein the gate contact is adjacent to and spaced apart from the permanent dummy gate;

wherein a dielectric cap region is between the permanent dummy gate and the gate contact;

wherein the permanent dummy gate, the dielectric cap region and the gate contact do not generate parasitic capacitance.