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Nanosheet transistor gate structure having reduced parasitic capacitance

  • US 10,615,256 B2
  • Filed: 06/27/2018
  • Issued: 04/07/2020
  • Est. Priority Date: 06/27/2018
  • Status: Active Grant
First Claim
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1. A method of fabricating a semiconductor device, the method comprising:

  • performing fabrication operations to form a nanosheet field effect transistor device on a substrate, wherein the fabrication operations include;

    forming a channel stack over the substrate, wherein the channel stack comprises stacked and spaced apart channel nanosheets;

    forming a metal gate located adjacent to end regions of the channel stack and further located around and between the stacked and spaced apart channel nanosheets; and

    forming a permanent dummy gate above the channel stack.

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