Nanosheet channel-to-source and drain isolation

• US 10,615,269 B2
• Filed: 08/21/2018
• Issued: 04/07/2020
• Est. Priority Date: 09/20/2016
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: Terresa Incorporated
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Lie, Fee Li, Miller, Eric R., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Menz, Laura M
• Application Number:
  US16/106,359
• Publication Number:
  US 20180374930A1
• Time in Patent Office: 595 Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H05K 999/99 dummy group

Abstract

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Claims

1. A structure used to fabricate a nanosheet semiconductor device, the structure comprising:

a substrate;

a set of silicon layers formed above the substrate, wherein the silicon layers of the set of silicon layers are parallel to each other and include gaps between adjacent ones of the silicon layers of the set of silicon layers, wherein each of the gaps defines a region that is parallel to the silicon layers of the set of silicon layers and extends from a first end to a second end of each of the adjacent ones of the silicon layers of the set of silicon layers;

an inner spacer at the first end and at the second end of each of the gaps between the adjacent ones of the silicon layers of the set of silicon layers; and

an oxide between the first end and the second end in each of the gaps between the adjacent ones of the silicon layers of the set of silicon layers.

2. The structure according to claim 1, wherein the inner spacer includes silicon nitride (SiN).

3. The structure according to claim 1, wherein the inner spacer is a low-k spacer.

4. The structure according to claim 3, wherein the low-k spacer includes silicon boron carbon nitride (SiBCN).

5. The structure according to claim 3, wherein the low-k spacer includes silicon oxycarbonitride (SiOCN).

6. The structure according to claim 3, wherein the low-k spacer includes silicon oxynitride (SiON).

7. The structure according to claim 1, further comprising doped silicon germanium adjacent to each side of the set of silicon layers and to the first end and the second end of each of the gaps between the adjacent ones of the silicon layers of the set of silicon layers.

8. The structure according to claim 7, wherein the doped silicon germanium is a source or a drain.

9. The structure according to claim 7, further comprising additional ones of the inner spacers adjacent to and opposite a side of the doped silicon germanium that is adjacent to the set of silicon layers.

10. The structure according to claim 7, further comprising silicon nitride (SiN) adjacent to and above the doped silicon germanium.

11. The structure according to claim 10, further comprising an oxide layer above the SiN.

12. The structure according to claim 11, wherein the oxide is an interlayer dielectric.