Integration scheme for non-volatile memory on gate-all-around structure

• US 10,615,288 B1
• Filed: 10/24/2018
• Issued: 04/07/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kong, Dexin, Bi, Zhenxing, Xu, Zheng, Cheng, Kangguo
• Primary Examiner(s): Sullivan, Caleen O
• Application Number:
  US16/169,207
• Publication Number:
  US 20200135937A1
• Time in Patent Office: 531 Days
• Field of Search: 257 4, 257324, 438382
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.

Claims

1. A method of performing integrated fabrication of a non-volatile memory (NVM) and a nanosheet field effect transistor (FET), the method comprising:

patterning fins for a channel region of the NVM and the nanosheet FET;

depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the nanosheet FET;

conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the nanosheet FET with the OPL and the block mask;

removing the OPL and the block mask protecting the fins for the channel region of the nanosheet FET;

forming source and drain regions of the NVM and the nanosheet FET; and

forming a gate of the nanosheet FET while protecting the NVM by depositing another OPL and another block mask.

2. The method according to claim 1, wherein the depositing the set of layers that make up the NVM structure includes conformally depositing silicon oxide nitride directly on the fins for the channel region of the NVM.

3. The method according to claim 2, wherein the depositing the set of layers that make up the NVM structure includes conformally depositing hafnium dioxide on the silicon oxide nitride.

4. The method according to claim 3, wherein the depositing the set of layers that make up the NVM structure includes conformally depositing silicon dioxide on the hafnium dioxide.

5. The method according to claim 1, wherein the patterning the fins for the channel region of the NVM includes patterning alternating silicon and silicon germanium layers.

6. The method according to claim 1, wherein the patterning the fins for the channel region of the NVM includes patterning a silicon germanium layer.

7. The method according to claim 1, further comprising performing an isotropic etch of the fins for the channel region of the NVM following the depositing the OPL and the block mask to protect the fins for the channel region of the nanosheet FET and prior to the conformally depositing the set of layers that make up the NVM structure.

8. The method according to claim 1, further comprising forming contacts to the source and drain regions of the NVM and the nanosheet FET.

9. The method according to claim 1, further comprising patterning polysilicon above the channel region of the NVM, wherein the polysilicon is part of the NVM structure along with silicon in the channel region of the NVM.

10. The method according to claim 9, further comprising forming contacts to the polysilicon.