Light emitting diode

• US 10,615,309 B2
• Filed: 09/18/2019
• Issued: 04/07/2020
• Est. Priority Date: 03/13/2017
• Status: Active Grant

• Current Assignee: AZUR SPACE Solar Power GmbH (5N Plus, Inc.)
• Original Assignee: AZUR SPACE Solar Power GmbH (5N Plus, Inc.)
• Inventors: Lauermann, Thomas, Koestler, Wolfgang, Fuhrmann, Bianca
• Primary Examiner(s): Blum, David S
• Application Number:
  US16/574,920
• Publication Number:
  US 20200013927A1
• Time in Patent Office: 202 Days
• Field of Search: 438 24, 438 32
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0062 for devices with an active region comprising only III-V compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/14 with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/30 containing only elements of Group III and Group V of the Periodic Table
• CPC Class Codes: H01L 33/38 with a particular shape

Abstract

A method for producing a light-emitting diode with a stacked structure, having a first region and a second region and a third region, wherein all three regions have a substrate and an n-doped lower cladding layer and an active layer generating electromagnetic radiation, wherein the active layer includes a quantum well structure, and a p-doped upper cladding layer, and the first region additionally has a tunnel diode formed on the upper cladding layer and composed of a p+ layer and an n+ layer, and an n-doped current distribution layer. The current distribution layer and the n-doped contact layer are covered with a conductive trace. At least the lower cladding layer, the active layer, the upper cladding layer, the tunnel diode, and the current distribution layer are monolithic in design. The second region has a contact hole with a bottom region.

Claims

1. A method for producing a light-emitting diode with a first region and a second region and a third region, the process comprising:

providing a stacked structure having a top and a bottom, composed of III-V semiconductor layers,

providing the stacked structure with a substrate forming the bottom, a lower cladding layer, an active layer generating electromagnetic radiation, and a quantum well structure, a p-doped upper cladding layer, a tunnel diode composed of a p⁺ layer and an n⁺ layer, an n-doped current distribution layer, and an n-doped contact layer, the p⁺ layer of the tunnel diode and the current distribution layer each including a III arsenide, the n⁺ layer of the tunnel diode including a III phosphide,

structuring a photosensitive layer on the top of the stacked structure during a masking process;

anisotropic etching of layers, starting from the top of the stacked structure in the second region to form a contact hole and etching of layers in the third region to create a texturing, the phosphide-containing n⁺ layer of the tunnel diode serving as an etch stop in each of the two regions during the etching;

forming a planar injection barrier in the bottom region of the contact hole;

depositing and structuring a conductive trace to fill the contact hole in the second region; and

forming terminal contact fingers in the first region.

2. The method according to claim 1, wherein the phosphide-containing n⁺ layer of the tunnel diode is removed at the bottom of the contact hole and in the recesses of the texturing.

3. The method according to claim 1, wherein at least one etching step is carried out via a wet etching using a peroxide/phosphoric acid.