Process for creating a high density magnetic tunnel junction array test platform
First Claim
1. A device, comprising:
- a grid of bit cells having a first density;
an array of pillars fabricated on a centrally located bit cell having a second density that is higher than the first density;
a bottom electrode layer comprising a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; and
a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a second fanout pattern.
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Abstract
A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.
496 Citations
24 Claims
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1. A device, comprising:
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a grid of bit cells having a first density; an array of pillars fabricated on a centrally located bit cell having a second density that is higher than the first density; a bottom electrode layer comprising a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; and a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a second fanout pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 23)
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8. A device, comprising:
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a grid of bit cells having a first density; an array of memory cell pillars fabricated on a centrally located bit cell having a second density that is higher than the first density; a bottom electrode layer comprising of a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a second fanout pattern; and a silicon oxide passivation layer on the surface of the device. - View Dependent Claims (9, 10, 11, 12, 13, 24)
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14. A device, comprising:
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a grid of bit cells having a first density; an array of memory cell pillars fabricated on a centrally located bit cell having a second density that is higher than the first density; a bottom electrode layer comprising a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell to a respective one of the grid of bit cells in a second fanout pattern; and a CMOS driving transistor for individually addressing each of the memory cell pillars. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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Specification