Circuit and method for suppressing audio noise in DC-DC converters

• US 10,615,694 B2
• Filed: 09/07/2018
• Issued: 04/07/2020
• Est. Priority Date: 09/07/2018
• Status: Active Grant

• Current Assignee: Dialog Semiconductors (UK) Limited
• Original Assignee: Dialog Semiconductors (UK) Limited
• Inventors: de Marco, Louis, Ozanoglu, Kemal, Ferner, Elke, Malinowski, Slawomir
• Primary Examiner(s): Moody, Kyle J
• Assistant Examiner(s): Quddus, Nusrat
• Application Number:
  US16/124,552
• Publication Number:
  US 20200083809A1
• Time in Patent Office: 578 Days
• CPC Class Codes: H02M 1/0035 using burst mode control
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A solution is provided for suppressing audio noise in a DC-DC switching converter. A means for limiting the minimum switching frequency of a pulse-frequency modulation (PFM) control is described. A first order gm amplifier dissipates the excess energy added to the inductor, when magnetizing at faster rate than the native PFM. A higher resistance, low-side scaled switch helps reduce wasted energy losses. The low-side scaled switch reduces the rise in the inductor current during magnetization, and hence keeps efficiency up at low loads, when the PFM minimum switching frequency is active.

Claims

1. An audio noise suppression circuit, in a DC-DC switching converter, comprising:

a first order gm amplifier, configured to sink excessive current from an output of the converter, and to receive a programmable voltage threshold on its inverting input and a switching converter output feedback voltage on its non-inverting input;

a low side device, connected between a node voltage and ground;

a low side scaled device, connected between the node voltage and ground; and

hysteretic Burst control logic, configured to generate bursts of on pulses to drive the low side device in a pulse-frequency mode (PFM),

and dummy pulses to drive a gate of the low side scaled device, for controlling the low side scaled device at a minimum switching frequency.

2. The circuit of claim 1, wherein a clock determines a period for said on pulses.

3. The circuit of claim 1, wherein said first order gm amplifier is configured to regulate said output feedback voltage.

4. The circuit of claim 1, wherein said first order gm amplifier has a power supply across said output feedback voltage and ground.

5. The circuit of claim 1, wherein said first order gm amplifier has a power supply across said output feedback voltage and said input voltage.

6. The circuit of claim 1, further comprising a voltage divider connected between said output feedback voltage and ground, configured to provide a feedback voltage.

7. The circuit of claim 6, further comprising an over voltage comparator configured to receive said feedback voltage on a non-inverting input.

8. The circuit of claim 6, further comprising an under voltage comparator configured to receive said feedback voltage on an inverting input.

9. The circuit of claim 1, wherein said low side device has its source connected to a source of said low side scaled device, and its drain to the node voltage.

10. The circuit of claim 1, wherein said on pulses drive a gate of said low side device.

11. The circuit of claim 1, further comprising an output capacitor connected at said output feedback voltage.

12. The circuit of claim 1, further comprising an inductor connected between said input voltage and said node voltage.

13. The circuit of claim 1, wherein said low side device and said low side scaled devices are NMOS type devices.

14. The circuit of claim 1, wherein the DC-DC switching converter has a period of switching activity configured to change with switching conditions and load current.

15. The circuit of claim 1, wherein the DC-DC switching converter is configured for a switching frequency of 20 kHz or higher.

16. The circuit of claim 1, wherein the DC-DC switching converter is a Boost switching converter.

17. The circuit of claim 1, wherein the DC-DC switching converter is a Buck-Boost or Buck switching converter.

18. The circuit of claim 1, wherein said first order gm amplifier is an operational transconductance amplifier (OTA).

19. The circuit of claim 1, wherein said dummy pulses have a frequency of 20 kHz or higher.

20. A method for suppressing audio noise, in a DC-DC switching converter, comprising:

detecting when said DC-DC switching converter is not switching, within a defined time-window;

utilizing dummy pulses to insure a minimum switching frequency higher than a predefined value, wherein said dummy pulses drive a gate of a scaled pass device; and

dissipating excess energy, added as a result of said dummy pulses, through a first order gm amplifier.

21. The method of claim 20, wherein said first order gm amplifier sinks current from an output of said DC-DC switching converter.

22. The method of claim 20, further comprising operating a low side pass device in pulse-frequency modulation (PFM).

23. The method of claim 20, wherein said DC-DC switching converter uses hysteretic control.

24. The method of claim 20, wherein said dummy pulses are longer than a propagation delay of logic plus level shifters plus drivers.

25. The method of claim 20, further comprising regulating an output voltage, using said first order gm amplifier, around a programmable overvoltage threshold.

26. The method of claim 20, wherein said minimum switching frequency is above an audio range.

27. The method of claim 20, wherein said minimum switching frequency is above 20 kHz.