Multi-stage reconfigurable triplexer

• US 10,616,053 B2
• Filed: 12/01/2016
• Issued: 04/07/2020
• Est. Priority Date: 12/04/2015
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Hou, Yang, Kasnavi, Reza, Ni, Jianxing, Zhao, Shanshan
• Primary Examiner(s): Skripnikov, Alex
• Assistant Examiner(s): Chowdhury, Sharmin
• Application Number:
  US15/366,435
• Publication Number:
  US 20170163298A1
• Time in Patent Office: 1,223 Days
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04B 1/0057 using diplexing or multiplexing filters for selecting the desired band
• CPC Class Codes: H04B 1/006 using switches for selecting the desired band H04B1/0057 takes precedence
• CPC Class Codes: H04L 41/0816 the condition being an adaptation, e.g. in response to network events
• CPC Class Codes: H04L 41/0823 characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability for optimising operational conditions of wireless networks H04W24/02

Abstract

A reconfigurable triplexer that can support more frequency bands than a traditional triplexer is disclosed. For example, the reconfigurable triplexer can handle frequencies of several hundred megahertz up to 10 gigahertz. Further, certain implementations of the reconfigurable multiplexer can reduce or eliminate frequency dead zones that exist with traditional multiplexers. The reconfigurable triplexer includes a multi-stage filter bank capable of supporting a number of frequency bands and a bypass circuit that enables the triplexer to support a variety of sets of frequencies. For instance, unlike traditional triplexers, the reconfigurable triplexer can support both frequency bands with relatively narrow spacing and frequency bands with relatively wide spacing. Further, the inclusion of the bypass circuit enables the reduction or elimination of dead zones between supported frequencies.

Claims

1. A triplexer comprising:

a first filter bank including one or more filters, the first filter bank in communication with an input port of the triplexer;

a plurality of load circuits configured to reduce insertion loss in a communication path between the input port of the triplexer and an output port of the triplexer;

a switch bank including a plurality of switches;

a second filter bank including one or more filters, the second filter bank positioned between the first filter bank and the switch bank, the plurality of switches connecting the one or more filters of the second filter bank to a load circuit from the plurality of load circuits; and

a plurality of bypass circuits between the first filter bank and the switch bank enabling a signal to bypass the second filter bank and be provided to the switch bank, at least one bypass circuit of the plurality of bypass circuits being of a first type and at least one other bypass circuit of the plurality of bypass circuits being of a second type that differs from the first type.

2. The triplexer of claim 1 wherein the first filter bank includes a low pass filter and a high pass filter.

3. The triplexer of claim 1 wherein the second filter bank includes a low pass filter and a high pass filter.

4. The triplexer of claim 1 wherein at least one filter of the first filter bank and at least one filter of the second filter bank are connected in cascade.

5. The triplexer of claim 1 wherein the first filter bank and the second filter bank do not include a band pass filter.

6. The triplexer of claim 1 wherein the first filter bank and the second filter bank are connected in series with one or more additional filter bank stages.

7. The triplexer of claim 1 wherein the switch bank selectively connects a filter from the second filter bank to the load circuit from the plurality of load circuits based at least in part on a control signal from a baseband processor.

8. The triplexer of claim 1 further comprising a bypass switch between the first filter bank and the plurality of bypass circuits.

9. The triplexer of claim 8 wherein the bypass switch is closed when a non-carrier aggregation signal is received.

10. The triplexer of claim 1 wherein a first filter from the first filter bank is connected to the switch bank without being connected to the second filter bank and a second filter from the first filter bank is connected to the second filter bank.

11. The triplexer of claim 1 wherein a first bypass circuit of the plurality of bypass circuits is configured with respect to a first frequency band, and a second bypass circuit of the plurality of bypass circuits is configured with respect to a second frequency band.

12. The triplexer of claim 1 wherein the at least one bypass circuit of the first type is a phase shift network.

13. The triplexer of claim 1 further comprising a plurality of input ports including the input port, each input port of the plurality of input ports configured to receive a signal of a different frequency band.

20. The triplexer of claim 1 further comprising at least one additional bypass circuit that is separate from the plurality of bypass circuits, the plurality of bypass circuits configured with respect to a first frequency band, and the at least one additional bypass circuit configured with respect to a second frequency band.

21. The triplexer of claim 1 wherein a switch in the switch bank connects at least one bypass circuit of the plurality of bypass circuits to a load circuit from the plurality of load circuits when a control signal associated with a carrier aggregation mode is received and connects the at least one bypass path to an output of the triplexer when a control signal associated with a non-carrier aggregation mode is received.

14. A transceiver comprising:

a power amplifier module including a plurality of power amplifiers; and

a triplexer in communication with the power amplifier module, the triplexer including a first filter bank, a second filter bank, a plurality of load circuits, a switch bank, and a plurality of bypass circuits, the first filter bank in communication with an input port and including one or more filters, the second filter bank positioned between the first filter bank and the switch bank and including one or more filters, the plurality of load circuits configured to reduce insertion loss in a communication path between the input port of the triplexer and an output port of the triplexer, the switch bank including a plurality of switches that connect the one or more filters of the second filter bank to a load circuit from the plurality of load circuits, and the plurality of bypass circuits positioned between the first filter bank and the switch bank enabling a signal to bypass the second filter bank and be provided to the switch bank, at least one bypass circuit of the plurality of bypass circuits being of a first type and at least one other bypass circuit of the plurality of bypass circuits being of a second type that differs from the first type.

15. The transceiver of claim 14 wherein the plurality of load circuits includes a first set of load circuits selectively connectable to the bypass circuit based on a control signal.

16. The transceiver of claim 14 wherein the plurality of load circuits includes a second set of load circuits selectively connectable to the second filter bank based on a control signal.

17. The transceiver of claim 14 wherein at least one filter of the first filter bank is connected in series with at least one filter of the second filter bank.

18. The transceiver of claim 14 wherein the first filter bank and the second filter bank omit a band pass filter.

19. A wireless device comprising:

a transceiver including a power amplifier module and a triplexer, the power amplifier module including a plurality of power amplifiers and the triplexer in communication with the power amplifier module, the triplexer including a first filter bank, a second filter bank, a plurality of load circuits, a switch bank, and a plurality of bypass circuits, the first filter bank in communication with an input port and including one or more filters, the second filter bank positioned between the first filter bank and the switch bank and including one or more filters, the plurality of load circuits configured to reduce insertion loss in a communication path between the input port of the triplexer and an output port of the triplexer, the switch bank including a plurality of switches that selectively connect the one or more filters of the second filter bank to a load circuit from the plurality of load circuits based on a control signal, and the plurality of bypass circuits positioned between the first filter bank and the switch bank enabling a signal to bypass the second filter bank and be provided to the switch bank, at least one bypass circuit of the plurality of bypass circuits being of a first type and at least one other bypass circuit of the plurality of bypass circuits being of a second type that differs from the first type; and

a baseband processor configured to provide the control signal to the triplexer, the control signal determined based at least in part on a communication from a base station.