Identifying a source of nuisance defects on a wafer

• US 10,620,135 B2
• Filed: 04/06/2018
• Issued: 04/14/2020
• Est. Priority Date: 07/19/2017
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Brauer, Bjorn
• Primary Examiner(s): Park, Soo Jin
• Application Number:
  US15/947,730
• Publication Number:
  US 20190025229A1
• Time in Patent Office: 739 Days
• Field of Search: None
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/9503 Wafer edge inspection
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/10061 from scanning electron microscope
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

Methods and systems for identifying a source of nuisance defects on a wafer are provided. One method includes detecting defects on a wafer by applying a hot threshold to output generated for the wafer by a detector of an inspection subsystem such that at least a majority of the detected defects include nuisance defects and determining locations of the detected defects with respect to design information for the wafer. In addition, the method includes stacking information for the detected defects based on the determined locations relative to a structure on the wafer such that the detected defects having the same locations relative to the structure are coincident with each other in results of the stacking. The method further includes identifying a source of the nuisance defects based on the results of the stacking.

Claims

1. A system configured to identify a source of nuisance defects on a wafer, comprising:

an inspection subsystem comprising at least an energy source and a detector, wherein the energy source is configured to generate energy that is directed to a wafer, and wherein the detector is configured to detect energy from the wafer and to generate output responsive to the detected energy; and

one or more computer subsystems configured for;

detecting defects on the wafer by applying a hot threshold to the output such that at least a majority of the detected defects comprise nuisance defects;

determining locations of the detected defects with respect to design information for the wafer;

stacking information for the detected defects based on the determined locations relative to a structure on the wafer such that the detected defects having the same locations relative to the structure are coincident with each other in results of the stacking; and

identifying a source of the nuisance defects based on the results of the stacking.

2. The system of claim 1, wherein the locations of the detected defects are determined with sub-pixel accuracy.

3. The system of claim 1, wherein the locations of the detected defects are determined by interpolation of the defect locations within the output and alignment of the output to the design information for the wafer.

4. The system of claim 1, wherein detecting the defects comprises generating difference images for different portions of the output by subtracting reference output for the different portions from the different portions of the output and applying the hot threshold to the difference images, and wherein determining the locations of the detected defects is performed by fitting a portion of the difference images corresponding to the detected defects to a function.

5. The system of claim 1, wherein the one or more computer subsystems are further configured for identifying the detected defects that are the nuisance defects by identifying areas in the stacking results in which a number of the detected defects located therein per unit area is greater than a predetermined threshold and designating the detected defects located in the identified areas as the nuisance defects.

6. The system of claim 1, wherein the structure on the wafer comprises a die on the wafer.

7. The system of claim 1, wherein the structure on the wafer comprises a printed instance of a reticle on the wafer.

8. The system of claim 1, wherein the structure on the wafer comprises patterned features formed on the wafer.

9. The system of claim 1, wherein identifying the source of the nuisance defects comprises identifying portions of the results of the stacking in which the results of the stacking and one or more of patterned features in two or more design layers for the wafer have spatial coincidence by comparing locations of the detected defects in the results of the stacking and locations of the patterned features in the two or more design layers and identifying the source of the nuisance defects as one of the two or more design layers comprising the one or more patterned features having spatial coincidence with the detected defects in the results of the stacking.

10. The system of claim 1, wherein the source of the nuisance defects comprises a design layer of the wafer.

11. The system of claim 1, wherein identifying the source of the nuisance defects comprises determining if the nuisance defects are caused by an uppermost layer on the wafer or a layer underlying the uppermost layer on the wafer.

12. The system of claim 1, wherein the nuisance defects comprise nuisance defects that are not visible to an electron beam based tool.

13. The system of claim 1, wherein the source of the nuisance defects comprises one or more patterned features on the wafer.

14. The system of claim 1, wherein the one or more computer subsystems are further configured for detecting other defects on the wafer by applying a defect detection threshold to the output such that at least a majority of the other defects do not comprise nuisance defects and noise, determining locations of the detected other defects with respect to the design information for the wafer, stacking information for the other defects based on the determined locations relative to a structure on the wafer such that the other defects having the same locations relative to the structure are coincident with each other in results of stacking the information for the other defects, and identifying a source of the other defects based on the results of stacking the information for the other defects.

15. The system of claim 1, wherein the one or more computer subsystems are further configured for verifying identification of the nuisance defects in the detected defects by selecting a portion of the nuisance defects for defect review and performing the defect review for the selected portion of the nuisance defects.

16. The system of claim 1, wherein the one or more computer subsystems are further configured for generating an inspection recipe for the wafer based on information for the source of the nuisance defects such that the nuisance defects are not detected in the inspection recipe.

17. The system of claim 1, wherein the inspection subsystem is configured as an optical inspection subsystem.

18. A non-transitory computer-readable medium, storing program instructions executable on a computer system for performing a computer-implemented method for identifying a source of nuisance defects on a wafer, wherein the computer-implemented method comprises:

detecting defects on the wafer by applying a hot threshold to output generated for the wafer by a detector of an inspection subsystem such that at least a majority of the detected defects comprise nuisance defects, wherein the inspection subsystem comprises at least an energy source and the detector, wherein the energy source is configured to generate energy that is directed to the wafer, and wherein the detector is configured to detect energy from the wafer and to generate the output responsive to the detected energy;

determining locations of the detected defects with respect to design information for the wafer;

stacking information for the detected defects based on the determined locations relative to a structure on the wafer such that the detected defects having the same locations relative to the structure are coincident with each other in results of the stacking; and

identifying a source of the nuisance defects based on the results of the stacking.

19. A computer-implemented method for identifying a source of nuisance defects on a wafer, comprising:

detecting defects on the wafer by applying a hot threshold to output generated for the wafer by a detector of an inspection subsystem such that at least a majority of the detected defects comprise nuisance defects, wherein the inspection subsystem comprises at least an energy source and the detector, wherein the energy source is configured to generate energy that is directed to the wafer, and wherein the detector is configured to detect energy from the wafer and to generate the output responsive to the detected energy;

determining locations of the detected defects with respect to design information for the wafer;

stacking information for the detected defects based on the determined locations relative to a structure on the wafer such that the detected defects having the same locations relative to the structure are coincident with each other in results of the stacking; and

identifying a source of the nuisance defects based on the results of the stacking, wherein said detecting, determining, stacking, and identifying are performed by one or more computer subsystems coupled to the inspection subsystem.