Apparatus and method for handling write operations

• US 10,621,103 B2
• Filed: 12/05/2017
• Issued: 04/14/2020
• Est. Priority Date: 12/05/2017
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Rose, Andrew Christopher, Grisenthwaite, Richard Roy, Saidi, Ali Ghassan
• Primary Examiner(s): Dudek, Jr., Edward J
• Assistant Examiner(s): Russell, Andrew
• Application Number:
  US15/831,609
• Publication Number:
  US 20190171573A1
• Time in Patent Office: 861 Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/163 Server or database system
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory. Further, the coherency circuitry is responsive to the clean operation to interact with the at least one further cache to implement a hardware protocol in order to make the write data visible to the at least one further processing device. This can provide a very efficient and cost effective mechanism for implementing cache coherency in certain systems.

Claims

1. An apparatus comprising:

a first processing device to execute a sequence of instructions, said sequence comprising at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region;

a writeback cache associated with the first processing device and arranged to store the write data output during the one or more write operations; and

coherency circuitry coupled to the writeback cache and to at least one further cache associated with at least one further processing device;

wherein;

the first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory;

the software protocol is arranged to regulate read access to the first memory region by the at least one further processing device during a period between establishment of the ownership right for the first processing device and performance of the clean operation; and

operation of the coherency circuitry is deferred until the clean operation is performed, wherein the coherency circuitry is responsive to the clean operation to interact with said at least one further cache to implement a hardware protocol in order to make the write data visible to said at least one further processing device.

2. An apparatus as claimed in claim 1, wherein the apparatus implements a cache coherency protocol in respect of the first memory region through a combination of the software protocol triggered by the first processing device and the hardware protocol implemented by the coherency circuitry.

3. An apparatus as claimed in claim 1, wherein the coherency circuitry is arranged, in response to the clean operation, to cause the at least one further cache to invalidate any cache entry whose content is associated with the at least one memory location of the write data.

4. An apparatus as claimed in claim 1, wherein:

said at least one further cache comprises a plurality of caches;

the coherency circuitry maintains a record providing, for each cache in said plurality, an indication of the memory locations whose data is cached by that cache; and

the coherency circuitry is arranged to reference the record when determining which caches amongst said plurality to interact with in order to make the write data visible to the at least one further processing device.

5. An apparatus as claimed in claim 4 wherein the coherency circuitry is snoop circuitry.

6. An apparatus as claimed in claim 1, further comprising:

lock storage to maintain lock indications for a number of memory regions; and

the software protocol is arranged, when activated by the first processing device, to determine whether a lock indication for the first memory region is clear, and in the event that the lock indication for the first memory region is clear, to set the lock indication for the first memory region and to identify to the first processing device that the first processing device has the ownership right for the first memory region.

7. An apparatus as claimed in claim 1, wherein upon notification from the coherency circuitry that the write data has been made visible to the at least one further processing device, the first processing device is arranged to release the ownership right.

8. An apparatus as claimed in claim 1, wherein the trigger event comprises one of:

execution by the first processing device of a cleaning instruction in the sequence that initiates the clean operation; and

an eviction event triggered in respect of an entry of the writeback cache containing the write data.

9. An apparatus as claimed in claim 8, wherein the cleaning instruction identifies a particular entry of the writeback cache whose data is to be cleaned.

10. An apparatus as claimed in claim 8, wherein the cleaning instruction triggers cleaning of multiple entries of the writeback cache, and the apparatus further comprises a storage unit to store information enabling the multiple entries to be identified.

11. An apparatus as claimed in claim 10, wherein:

the storage unit is arranged to store indications of the write operations performed by the first processing device;

the cleaning instruction is an end instruction in the sequence of instructions, and the first processing device is responsive to execution of the end instruction by;

causing the write data that is the subject of each write operation for which an indication is stored in the storage unit to be cleaned from the write-back cache to the memory; and

clearing the indications of the write operations stored in the storage unit.

12. An apparatus as claimed in claim 11, wherein the memory is non-volatile memory forming a point of persistence, and execution of the end instruction causes the write data to be propagated to the point of persistence.

13. An apparatus as claimed in claim 11, wherein the first processing device is further arranged to cause the indications of the write operations performed by the first processing device to be stored in the storage unit after a begin instruction in the sequence of instructions.

14. An apparatus as claimed in claim 13, wherein the first processing device is arranged to only perform a write operation to the first memory region when the ownership right for writing data to the first memory region has been established, and a pending write instruction specifying a memory location within the first memory region is preceded by the begin instruction and followed by the end instruction.

15. An apparatus as claimed in claim 2, wherein for at least one further memory region, the cache coherency protocol is implemented solely by the coherency circuitry, and the first processing device is arranged to obtain exclusive write access to the at least one further memory region via steps performed by the coherency circuitry in respect of the at least one further cache.

16. A method of handling write operations in an apparatus having a first processing device, a writeback cache associated with the first processing device, and coherency circuitry coupled to the writeback cache and to at least one further cache associated with at least one further processing device, the method comprising:

executing on the first processing device at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region;

storing within the writeback cache the write data output during the one or more write operations;

responsive to a trigger event, causing the first processing device to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory;

employing the software protocol to regulate read access to the first memory region by the at least one further processing device during a period between establishment of the ownership right for the first processing device and performance of the clean operation;

deferring operation of the coherency circuitry until the clean operation is performed; and

responsive to the clean operation, causing the coherency circuitry to interact with said at least one further cache to implement a hardware protocol in order to make the write data visible to said at least one further processing device.

17. An apparatus comprising:

first processing means for executing a sequence of instructions, said sequence comprising at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region;

a writeback cache means associated with the first processing means, for storing the write data output during the one or more write operations; and

coherency means for coupling to the writeback cache means and to at least one further cache means associated with at least one further processing means;

wherein;

the first processing means, responsive to a trigger event, for initiating a clean operation in order to cause the write data to be written from the writeback cache means to memory;

the software protocol is arranged to regulate read access to the first memory region by the at least one further processing means during a period between establishment of the ownership right for the first processing means and performance of the clean operation; and

operation of the coherency means is deferred until the clean operation is performed, wherein the coherency means is responsive to the clean operation, arranged to interacting with said at least one further cache means to implement a hardware protocol in order to make the write data visible to said at least one further processing means.