Apparatus and method for handling write operations
First Claim
1. An apparatus comprising:
- a first processing device to execute a sequence of instructions, said sequence comprising at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region;
a writeback cache associated with the first processing device and arranged to store the write data output during the one or more write operations; and
coherency circuitry coupled to the writeback cache and to at least one further cache associated with at least one further processing device;
wherein;
the first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory;
the software protocol is arranged to regulate read access to the first memory region by the at least one further processing device during a period between establishment of the ownership right for the first processing device and performance of the clean operation; and
operation of the coherency circuitry is deferred until the clean operation is performed, wherein the coherency circuitry is responsive to the clean operation to interact with said at least one further cache to implement a hardware protocol in order to make the write data visible to said at least one further processing device.
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Abstract
An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory. Further, the coherency circuitry is responsive to the clean operation to interact with the at least one further cache to implement a hardware protocol in order to make the write data visible to the at least one further processing device. This can provide a very efficient and cost effective mechanism for implementing cache coherency in certain systems.
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Citations
17 Claims
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1. An apparatus comprising:
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a first processing device to execute a sequence of instructions, said sequence comprising at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region; a writeback cache associated with the first processing device and arranged to store the write data output during the one or more write operations; and coherency circuitry coupled to the writeback cache and to at least one further cache associated with at least one further processing device; wherein; the first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory; the software protocol is arranged to regulate read access to the first memory region by the at least one further processing device during a period between establishment of the ownership right for the first processing device and performance of the clean operation; and operation of the coherency circuitry is deferred until the clean operation is performed, wherein the coherency circuitry is responsive to the clean operation to interact with said at least one further cache to implement a hardware protocol in order to make the write data visible to said at least one further processing device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of handling write operations in an apparatus having a first processing device, a writeback cache associated with the first processing device, and coherency circuitry coupled to the writeback cache and to at least one further cache associated with at least one further processing device, the method comprising:
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executing on the first processing device at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region; storing within the writeback cache the write data output during the one or more write operations; responsive to a trigger event, causing the first processing device to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory; employing the software protocol to regulate read access to the first memory region by the at least one further processing device during a period between establishment of the ownership right for the first processing device and performance of the clean operation; deferring operation of the coherency circuitry until the clean operation is performed; and responsive to the clean operation, causing the coherency circuitry to interact with said at least one further cache to implement a hardware protocol in order to make the write data visible to said at least one further processing device.
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17. An apparatus comprising:
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first processing means for executing a sequence of instructions, said sequence comprising at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region; a writeback cache means associated with the first processing means, for storing the write data output during the one or more write operations; and coherency means for coupling to the writeback cache means and to at least one further cache means associated with at least one further processing means; wherein; the first processing means, responsive to a trigger event, for initiating a clean operation in order to cause the write data to be written from the writeback cache means to memory; the software protocol is arranged to regulate read access to the first memory region by the at least one further processing means during a period between establishment of the ownership right for the first processing means and performance of the clean operation; and operation of the coherency means is deferred until the clean operation is performed, wherein the coherency means is responsive to the clean operation, arranged to interacting with said at least one further cache means to implement a hardware protocol in order to make the write data visible to said at least one further processing means.
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Specification