Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating
First Claim
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1. A single polysilicon floating gate semiconductor memory cell comprising:
- a substrate;
a floating body region exposed at a surface of said substrate and configured to store volatile memory;
a single polysilicon floating gate configured to store nonvolatile data;
an insulating region insulating said floating body region from said single polysilicon floating gate; and
first and second regions exposed at said surface at locations other than where said floating body region is exposed;
wherein said single polysilicon floating gate is configured to receive transfer of data stored as said volatile memory by said floating body region; and
wherein charge is stored into said floating body region upon restoration of power to said memory cell, and is non-algorithmically determined by charge stored in said single polysilicon floating gate.
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
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Citations
21 Claims
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1. A single polysilicon floating gate semiconductor memory cell comprising:
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a substrate; a floating body region exposed at a surface of said substrate and configured to store volatile memory; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating said floating body region from said single polysilicon floating gate; and first and second regions exposed at said surface at locations other than where said floating body region is exposed; wherein said single polysilicon floating gate is configured to receive transfer of data stored as said volatile memory by said floating body region; and wherein charge is stored into said floating body region upon restoration of power to said memory cell, and is non-algorithmically determined by charge stored in said single polysilicon floating gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A single polysilicon floating gate semiconductor memory cell comprising:
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a substrate; a floating body region exposed at a surface of said substrate and configured to store volatile memory; a buried layer buried in a bottom portion of said substrate; wherein applying a bias to said buried layer results in at least two stable floating body region charge levels; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating said floating body region from said single polysilicon floating gate; and first and second regions exposed at said surface at locations other than where said floating body region is exposed; wherein said single polysilicon floating gate is configured to receive transfer of data stored as said volatile memory by said floating body region; and wherein charge is stored into said floating body region upon restoration of power to said single polysilicon floating gate semiconductor memory cell, and is non-algorithmically determined by charge stored in said single polysilicon floating gate. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification