System controller and method for determining the location of the most current data file stored on a plurality of memory circuits

• US 10,622,078 B2
• Filed: 08/21/2018
• Issued: 04/14/2020
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Norman, Robert D., Harari, Eli
• Primary Examiner(s): Leboeuf, Jerome
• Application Number:
  US16/107,306
• Publication Number:
  US 20190006015A1
• Time in Patent Office: 602 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/92 Capacitors having potential barriers
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory circuit that is organized into memory pages includes control circuitry for (a) associating a designated one or more memory pages to a data file and associating with the data file a unique identifier index number generated by a system controller; and associating a time-stamp with the unique identifier index number every time the data file is stored or updated in the memory circuit, wherein all unique identifier index numbers for all files stored in the memory circuit are stored in a lookup table in the memory circuit with the latest time-stamp and the location in the memory circuit at which the file is stored.

Claims

1. A method for a system controller to rapidly determine the location of the most current version of a data file stored on one of many memory circuits, comprising:

in each memory circuit;

(a) associating a designated one or more pages of the data file with a unique identifier index number generated by the system controller and appending the unique identifier index number to the data file; and

(b) associating a time-stamp with the unique identifier index number every time the data file is stored or updated in the memory circuit, wherein all unique identifier index numbers for all files stored in each memory circuit are stored in a lookup table in the memory circuit with the latest time-stamp and the location in the memory circuit at which the file is stored;

sending from the system controller a search request which is broadcast simultaneously to one or more of the memory circuits, the search request specifying unique identifier index number of the file to be located; and

in each memory circuit, using exclusive-or (XOR) circuits or content addressable memory (CAM) circuits to compare the broadcasted unique identifier index number with the unique identifier index numbers stored in the look-up table of the memory circuit and reporting to the system controller when a match has been found along with its time-stamp and location, wherein when more than one match is found, the system controller selects from the reported locations the location whose associated time-stamp is the latest among the time-stamps reported.

2. The method of claim 1, wherein each memory circuit comprises a portion which is configured to operate as a low read-latency cache memory, and wherein the look-up table is stored in the cache memory.

3. The method of claim 1, wherein each memory circuit comprises a data integrity circuit which, upon detecting an error in the memory circuit, communicates the error to an on-chip error-correcting circuitry or to the system controller, thereby enabling the on-chip error-correcting circuitry or the system controller to carry out a data recovery and program-refresh operation.

4. The method of claim 1, wherein each memory circuit comprises an interface circuit that allows direct access to the memory circuit using one or more conventional DRAM, SRAM, NOR flash, NAND flash, Flash solid state drive, word-wide or serial bit steaming protocols.

5. The method of claim 1, further comprising, in each memory circuit, performing a read-refresh or program-refresh operation on a portion of the memory circuit in a background mode, while carrying out concurrently read, program, or erase operations in a second portion of the memory circuit and powering down a third portion of the memory circuit.

6. The method of claim 1, further comprising storing on-chip resource management data in each memory circuit, the on-chip resource management data includes one or more of:

an updatable file allocation table for files stored in the memory circuit, a program/erase cycle count, chip temperature, and a time-stamp that is appended to each stored data file when it is updated.

7. The method of claim 1, further comprising providing, in each memory circuit, a pipeline streaming circuitry that overlaps sensing a memory page of stored data in sense amplifiers and transferring the sensed data to a data buffer for serial bit stream, or parallel word-wide output from the memory circuit, with concurrently reading a next memory page of the stored data from the memory structure for sensing in the sense amplifies.

8. The method of claim 7, wherein the data buffer is provided between portions of the memory circuit that operates under different speeds.

9. A memory circuit organized into a plurality of memory pages, comprising:

control circuitry for (a) associating a designated one or more memory pages to a data file and associating with the data file a unique identifier index number generated by a system controller; and

associating a time-stamp with the unique identifier index number every time the data file is stored or updated in the memory circuit, wherein all unique identifier index numbers for all files stored in the memory circuit are stored in a lookup table in the memory circuit with the latest time-stamp and the location in the memory circuit at which the file is stored; and

circuitry for concurrently carrying out (i) a read-refresh or program-refresh operation on a portion of the memory circuit in a background mode, (ii) read, program, or erase operations in a second portion of the memory circuit and (iii) powering down a third portion of the memory circuit.

10. The memory circuit of claim 9, wherein the control circuitry comprises exclusive-or (XOR) circuits or content addressable memory (CAM) circuits for comparing the unique identifier index number of a data file to be located sent from the system controller with the unique identifier index numbers stored in the look-up table and wherein the control circuitry reports to the system controller when a match is found, sending along a time-stamp and a location of the data file found matching.

11. The memory circuit of claim 9, wherein the memory circuit further comprises a portion which is configured to operate as a low read-latency cache memory, and wherein the look-up table is stored in the cache memory.

12. The memory circuit of claim 9, wherein the memory circuit further comprises a data integrity circuit which, upon detecting an error in the memory circuit, communicates the error to an on-chip error-correcting circuitry or to the system controller, thereby enabling the on-chip error-correcting circuitry or the system controller to carry out a data recovery and program-refresh operation.

13. The memory circuit of claim 9, wherein the memory circuit further comprises an interface circuit that allows direct access to the memory circuit using one or more conventional DRAM, SRAM, NOR flash, NAND flash, Flash solid state drive, word-wide or serial bit steaming protocols.

14. The memory circuit of claim 9, further comprising storage for on-chip resource management data, the on-chip resource management data includes one or more of:

an updatable file allocation table for files stored in the memory circuit, a program/erase cycle count, chip temperature, and a time-stamp that is appended to each stored data file when it is updated.

15. The memory circuit of claim 9, further comprising pipeline streaming circuitry that overlaps sensing a memory page of stored data in sense amplifiers and transferring the sensed data to a data buffer for serial bit stream, or parallel word-wide output from the memory circuit, with concurrently reading a next memory page of the stored data from the memory structure for sensing in the sense amplifies.

16. The memory circuit of claim 15, wherein the data buffer is provided between portions of the memory circuit that operates under different speeds.