Semiconductor device having SOI substrate and first and second diffusion layer

• US 10,622,263 B2
• Filed: 01/12/2018
• Issued: 04/14/2020
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Arai, Yasuo, Okihara, Masao, Kasai, Hiroki
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/870,503
• Publication Number:
  US 20180138232A1
• Time in Patent Office: 823 Days
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claims

1. A semiconductor device, comprising:

a silicon on insulator (SOI) substrate that includes a first surface;

a first semiconductor layer that includes a second surface opposite to the first surface, and a third surface opposite to the second surface, the third surface having a semiconductor element disposed thereon;

a first oxide film layer that is formed in contact with the first surface and the second surface;

a second oxide film layer that covers the third surface and the semiconductor element;

a first diffusion layer that is formed on the first surface, the first diffusion layer, in a plan view, including and overlapping with a region on the first surface that corresponds to the first semiconductor layer when the first semiconductor layer is as seen in the plan view;

a first electrode that is connected to a first reference potential and that penetrates through the first oxide film layer and the second oxide film layer to connect to the first diffusion layer; and

a diode including;

a second diffusion layer that is connected to a second reference potential and that is formed in a part of a region of the first surface corresponding to a region that is adjacent to the first diffusion layer in the plan view; and

a second semiconductor layer that is formed to be co-planar with the first semiconductor layer in a cross-sectional view, a region of the second semiconductor layer corresponding to the first surface being disposed in a region that is sandwiched between the first diffusion layer and the second diffusion layer in the plan view.

2. The semiconductor device according to claim 1, further comprising:

a third diffusion layer that is formed on the first surface, and that is disposed in a region that is sandwiched between a region corresponding to the first semiconductor layer and a region corresponding to the second semiconductor layer in the plan view.

3. The semiconductor device according to claim 2, wherein the third diffusion layer is connected to the first reference potential.

4. The semiconductor device according to claim 2, further comprising:

a fourth diffusion layer formed on the first surface, and that is sandwiched between the region corresponding to the first semiconductor layer and a region corresponding to the third diffusion layer in the plan view.

5. The semiconductor device according to claim 4, wherein

the fourth diffusion layer is connected to the second reference potential.