Nanosheet devices with different types of work function metals

• US 10,622,264 B2
• Filed: 05/28/2019
• Issued: 04/14/2020
• Est. Priority Date: 03/28/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Miao, Xin, Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): Sullivan, Caleen O
• Application Number:
  US16/423,364
• Publication Number:
  US 20190304848A1
• Time in Patent Office: 322 Days
• Field of Search: 257392
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A technique relates to a semiconductor device. A first work function metal is in first stack and second stacks, each having nanowires separated by the first work function metal. A mask is on the first stack such that the first work function metal in the first stack is protected while the first work function metal in the second stack is exposed. The mask is undercut by removing a portion of first work function metal in first stack, leaving a gap. A plug is formed in the gap underneath the mask so as to protect the first work function metal in first stack. First work function metal in the second stack is removed, thereby removing the first work function metal from in between the nanowires of the second stack. The mask and plug are removed from first stack. A second work function metal is formed on first and second stacks.

Claims

1. A semiconductor device comprising:

a first stack comprising a first two or more nanowires, a first work function metal on the first two or more nanowires, and a second work function metal in direct contact with and on the first work function metal, wherein the first two or more nanowires are separated by the first work function metal; and

a second stack comprising a second two or more nanowires and the second work function metal, wherein the second two or more nanowires are separated by the second work function metal.

2. The semiconductor device of claim 1, wherein the second work function metal is formed on top of the first work function metal in the first stack.

3. The semiconductor device of claim 1, wherein the second work function metal is not formed in between the first two or more nanowires in the first stack.

4. The semiconductor device of claim 1, wherein a dielectric material is formed around the first two or more nanowires.

5. The semiconductor device of claim 4, wherein the dielectric material comprises a dielectric constant greater than 4.0.

6. The semiconductor device of claim 4, wherein the dielectric material comprises a dielectric constant greater than 7.0.

7. The semiconductor device of claim 4, wherein the dielectric material comprises a dielectric constant greater than 10.0.

8. The semiconductor device of claim 1, wherein a dielectric material is sandwiched between the first work function metal and the first two or more nanowires.

9. The semiconductor device of claim 1, wherein a dielectric material is formed around the second two or more nanowires.

10. The semiconductor device of claim 9, wherein the dielectric material comprises a dielectric constant greater than 4.0.

11. The semiconductor device of claim 9, wherein the dielectric material comprises a dielectric constant greater than 7.0.

12. The semiconductor device of claim 9, wherein the dielectric material comprises a dielectric constant greater than 10.0.

13. The semiconductor device of claim 1, wherein a dielectric material is sandwiched between the first work function metal and the second two or more nanowires.

14. The semiconductor device of claim 1, wherein the first work function metal and the second work function metal are different.

15. The semiconductor device of claim 1, wherein the first work function metal comprises a p-type work function metal and the second work function metal comprises an n-type work function metal.

16. The semiconductor device of claim 1, wherein the first work function metal comprises an n-type work function metal and the second work function metal comprises a p-type work function metal.

17. The semiconductor device of claim 1, wherein a step is between the first stack and the second stack.

18. The semiconductor device of claim 17, wherein the step is formed by the second work function metal in the first stack overlapping the second work function metal in the second stack.

19. The semiconductor device of claim 1, wherein the first stack and the second stack are formed on a substrate.

20. The semiconductor device of claim 19, wherein isolation material separates the first stack and the second stack from the substrate.