Multi terminal capacitor within input output path of semiconductor package interconnect

• US 10,622,299 B2
• Filed: 02/07/2019
• Issued: 04/14/2020
• Est. Priority Date: 07/11/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arvin, Charles L., Audet, Jean, Quinlan, Brian W., Reynolds, Charles L., Sundlof, Brian R.
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US16/269,730
• Publication Number:
  US 20190172784A1
• Time in Patent Office: 432 Days
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H05K 1/0231 : Capacitors or dielectric substances
• CPC Class Codes: H05K 2201/10015 : Non-printed capacitor

Abstract

An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

Claims

1. An integrated circuit (IC) device comprising:

a first contact that neighbors a second contact;

a patterned mask comprising a first opening that exposes a first area of the first contact and a second opening that exposes a first area of the second contact;

the patterned mask further comprising a first capacitor tab that consists of an extension of the first opening that directionally extends toward the second contact and further exposes an additional second area of the first contact; and

the patterned mask further comprising a second capacitor tab that consists of an extension of the second opening that directionally extends toward the first contact and further exposes an additional second area of the second contact.

2. The IC device of claim 1, wherein the first capacitor tab is aligned with the second capacitor tab.

3. The IC device of claim 1, further comprising:

a multi terminal capacitor comprising a first terminal directly connected to the additional second area of the first contact and a second terminal directly connected to the additional second area of the second contact.

4. The IC device of claim 3, wherein the patterned mask further comprises a mask portion between the neighboring first contact and the second contact.

5. The IC device of claim 4, wherein the mask portion between the neighboring first contact and the second contact comprises a surface facing the multi terminal capacitor that is below a major top surface of the mask.

6. The IC device of claim 4, further comprising adhesive that connects the multi terminal capacitor with the mask portion.

7. The IC device of claim 3, further comprising a first solder interconnect that contacts at least the first area of the first contact and a second solder interconnect that contacts at least the first area of the second contact.

8. The IC device of claim 7, wherein the first solder interconnect further connects the first terminal to the additional second area of the first contact and wherein the second solder interconnect further connects the second terminal to the additional second area of the second contact.

9. The IC device of claim 8, wherein there is no inductance between the first solder interconnect and the first terminal and wherein there no inductance between the first solder interconnect and the additional second area of the first contact.

10. The IC device of claim 9, wherein there is no inductance between the second solder interconnect and the second terminal and wherein there no inductance between the second solder interconnect and the additional second area of the second contact.

11. An integrated circuit (IC) device fabrication method comprising:

patterning a mask to form a first opening that exposes a a first area of a first contact;

patterning the mask to form a second opening that exposes a first area of a second contact, the second contact neighboring the first contact;

patterning the mask to form a first capacitor tab that consists of an extension of the first opening that directionally extends toward the second contact and further exposes an additional second area of the first contact; and

patterning the mask to form a second capacitor tab that consists of an extension of the second opening that directionally extends toward the first contact and further exposes an additional second area of the second contact.

12. The IC device fabrication method of claim 11, wherein the first capacitor tab is aligned with the second capacitor tab.

13. The IC device fabrication method of claim 11, further comprising:

connecting a first terminal of a multi terminal capacitor to additional second area of the first contact; and

connecting a second terminal of the multi terminal capacitor to the additional second area of the second contact.

14. The IC device fabrication method of claim 13, wherein the mask is patterned further to retain a mask portion between the neighboring first contact and the second contact.

15. The IC device fabrication method of claim 14, wherein the mask portion between the neighboring first contact and the second contact comprises a surface facing the multi terminal capacitor that is below a major top surface of the mask.

16. The IC device fabrication method of claim 14, further comprising:

forming an adhesive upon the mask portion; and

connecting the multi terminal capacitor and the mask portion with the adhesive between the neighboring first contact and the second contact.

17. The IC device fabrication method of claim 13, further comprising:

forming a first solder interconnect upon at least the first area of the first contact; and

forming a second solder interconnect upon at least the first area of the second contact.

18. The IC device fabrication method of claim 17, further comprising:

reflowing the first solder interconnect to connect the first terminal to the additional second area of the first contact; and

reflowing the second solder interconnect to connect the second terminal to the on additional second area of the second contact.

19. The IC device fabrication method of claim 18, wherein there no inductance between the first solder interconnect and the first terminal and wherein there no inductance between the additional second area of the first solder interconnect and the first contact.

20. The IC device fabrication method of claim 19, wherein there no inductance between the second solder interconnect and the second terminal and wherein there no inductance between the second solder interconnect and the additional second area of the second contact.