Method of processing a substrate and a device manufactured by using the method

• US 10,622,375 B2
• Filed: 11/13/2018
• Issued: 04/14/2020
• Est. Priority Date: 11/07/2016
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Chun, Seung Ju, Yoo, Yong Min, Choi, Jong Wan, Kim, Young Jae, Kim, Sun Ja, Lim, Wan Gyu, Min, Yoon Ki, Lee, Hae Jin, Yoo, Tae Hee
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Joy, Jeremy J
• Application Number:
  US16/188,690
• Publication Number:
  US 20190081072A1
• Time in Patent Office: 518 Days
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/4554 Plasma being used non-continuously in between ALD reactions C23C16/56 takes precedence
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

Claims

1. A method of processing a substrate, the method comprising:

forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface;

forming a second layer on the first layer, the second layer being formed of the same material as a material for the first layer; and

performing an isotropic etching process on the first layer and the second layer,

wherein, during the isotropic etching process, an etch rate of a portion of the second layer on the side surface is greater than an etch rate of portions of the second layer on the upper and lower surfaces, and

wherein the method further comprises selectively densifying the second layer.

2. The method of claim 1, wherein the densifying is performed via an asymmetric plasma application.

3. The method of claim 1, wherein the second layer is selectively densified through a post-plasma treatment after the forming the second layer.

4. The method of claim 1, wherein the second layer is selectively densified during the forming the second layer.

5. The method of claim 4, wherein a plasma is applied during the forming the second layer, and

wherein a directivity of the plasma is controlled to control a feature of the second layer according to positions of the stepped structure.

6. A method of processing a substrate, the method comprising:

forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface;

forming a second layer on the first layer, the second layer being formed of the same material as a material for the first layer; and

performing an isotropic etching process on the first layer and the second layer,

wherein, during the isotropic etching process, an etch rate of a portion of the second layer on the side surface is greater than an etch rate of portions of the second layer on the upper and lower surfaces, and

wherein a flow rate of a hydrogen-containing gas used in the forming of the second layer is less than a flow rate of a hydrogen-containing gas used in the forming of the first layer.

7. A method of processing a substrate, the method comprising:

forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface;

forming a second layer on the first layer, the second layer being formed of the same material as a material for the first layer; and

performing an isotropic etching process on the first layer and the second layer,

wherein, during the isotropic etching process, an etch rate of a portion of the second layer on the side surface is greater than an etch rate of portions of the second layer on the upper and lower surfaces, and

wherein a hydrogen content of the second layer is less than a hydrogen content of the first layer.

8. A method of processing a substrate, the method comprising:

forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface,

wherein portions of the at least one layer respectively on the upper surface and the lower surface except for the side surface are selectively densified via an asymmetric plasma application.

9. The method of claim 8, further comprising:

performing an isotropic etching process on the at least one layer,

wherein, during the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

10. The method of claim 8, wherein the at least one layer is formed through a PEALD process using the asymmetric plasma application.

11. The method of claim 10, wherein the PEALD process a cycle including source feeding, purging, reactant feeding, RF plasma, and purging, and

wherein the asymmetric plasma application is achieved by the RF plasma.

12. A method of processing a substrate, the method comprising:

a first SiN thin film deposition step to form a first silicon nitride layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface;

a second PEALD SiN thin film deposition step to form a second nitride layer on the first silicon nitride layer; and

a wet etching step after the second PEALD thin film deposition step,

wherein plasma having directivity is applied in the second PEALD SiN thin film deposition step.

13. The method of claim 12, wherein a nitrogen content of the second silicon nitride layer is greater than a nitrogen content of the first silicon nitride layer.