Transistors with dual gate conductors, and associated methods

• US 10,622,452 B2
• Filed: 06/05/2018
• Issued: 04/14/2020
• Est. Priority Date: 06/05/2018
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Castro, Tom K., Zuniga, Marco A., Fatemizadeh, Badredin, Brand, Adam, Xia, John, Singh, Rajwinder, Xu, Min, Ni, Chi-Nung
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US16/000,719
• Publication Number:
  US 20190371902A1
• Time in Patent Office: 679 Days
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/945 : Trench capacitors
• CPC Class Codes: H02M 3/158 : including plural semiconductor devices as final control devices for a single load

Abstract

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.

Claims

1. A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor, comprising:

a silicon semiconductor structure; and

a vertical gate, including;

a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction,

a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate in each of the thickness direction and a lateral direction, the lateral direction being orthogonal to the thickness direction, and

a gate dielectric layer separating each of first the gate conductor and the second gate conductor from the silicon semiconductor structure, wherein;

the gate dielectric layer separates the first gate conductor from a first source region of the LDMOS transistor by a separation distance t₂ in the lateral direction,

the gate dielectric layer separates the second gate conductor from the first source region of the LDMOS transistor by a separation distance t₃ in the lateral direction, and

the separation distance t₂ is greater than the separation distance t₃.

2. The LDMOS transistor of claim 1, wherein the first gate conductor is adjacent to a drain region of the LDMOS transistor in the lateral direction.

3. The LDMOS transistor of claim 2, wherein the second gate conductor is adjacent to the first source region of the LDMOS transistor in the lateral direction.

4. The LDMOS transistor of claim 1, wherein:

the silicon semiconductor structure includes;

a base layer,

an n-type layer disposed over the base layer in the thickness direction,

a p-body region disposed in the n-type layer,

a source n+ region disposed in the p-body region, and

a drain n+ region disposed in the n-type layer; and

each of the first gate conductor and the second gate conductor is disposed between the source n+ region and the drain n+ region in the lateral direction.

5. The LDMOS transistor of claim 4, further comprising:

a source electrode electrically coupled to the source n+region;

a drain electrode electrically coupled to the drain n+region; and

a first gate electrode electrically coupled to the first gate conductor.

6. The LDMOS transistor of claim 5, wherein the first gate electrode is additionally electrically coupled to the second gate conductor.

7. The LDMOS transistor of claim 5, further comprising a second gate electrode electrically coupled to the second gate conductor.

8. The LDMOS transistor of claim 4, further comprising a p-type reduced surface field effect (RESURF) layer disposed below the vertical gate in the thickness direction.

9. The LDMOS transistor of claim 1, wherein the vertical gate further includes:

a third gate conductor; and

a second separation dielectric layer separating the first gate conductor from the third gate conductor within the vertical gate.

10. The LDMOS transistor of claim 9, wherein the second separation dielectric layer separates the first gate conductor from the third gate conductor in the thickness direction.

11. The LDMOS transistor of claim 9, wherein the gate dielectric layer further separates the third gate conductor from the silicon semiconductor structure.

12. The LDMOS transistor of claim 9, wherein:

the first gate conductor is adjacent to a drain region of the LDMOS transistor in the lateral direction;

the second gate conductor is adjacent to the first source region of the LDMOS transistor in the lateral direction; and

the third gate conductor is adjacent to a well region of the LDMOS transistor in the thickness direction.

13. An integrated circuit, comprising:

the LDMOS transistor of claim 1; and

a trench capacitor, including;

a first capacitor conductor and a second capacitor conductor each extending from the first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in the thickness direction, and

a capacitor dielectric layer separating each of the first capacitor conductor and the second capacitor conductor from the silicon semiconductor structure.

14. The integrated circuit of claim 13, further comprising a spacer dielectric layer separating the first capacitor conductor from the second capacitor conductor within the vertical gate.

15. The integrated circuit of claim 13, further comprising driver circuitry configured to drive the vertical gate of the LDMOS transistor, wherein:

the driver circuitry is powered from a first power rail; and

the trench capacitor is electrically coupled across the first power rail.