Integrated circuit structure with substrate isolation and un-doped channel

• US 10,622,464 B2
• Filed: 12/14/2018
• Issued: 04/14/2020
• Est. Priority Date: 09/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Chen, Guan-Lin
• Primary Examiner(s): Whalen, Daniel
• Application Number:
  US16/220,297
• Publication Number:
  US 20190123180A1
• Time in Patent Office: 487 Days
• Field of Search: None
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Integrated circuit devices, such as fin-like field effect transistors, and methods of fabricating thereof are disclosed herein. An exemplary device includes a fin that includes a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer. The second semiconductor layer includes a partially oxidized portion and a completely oxidized portion. A third semiconductor layer is disposed on the partially oxidized portion of the second semiconductor layer, where a source region and a drain region are defined in the third semiconductor layer. A fourth semiconductor layer is disposed on the completely oxidized portion of the second semiconductor layer, where a channel region is defined in the fourth semiconductor layer between the source region and the drain region defined in the third semiconductor layer. A gate structure is disposed over the channel region defined in the fourth semiconductor layer of the fin.

Claims

1. A device comprising:

a fin structure that includes a first material portion disposed between second material portions, wherein the first material portion includes;

a first semiconductor oxide layer having a first thickness, and

a first semiconductor layer disposed on the first semiconductor oxide layer, and

further wherein the second material portions include;

a second semiconductor oxide layer having a second thickness, wherein the first thickness is greater than the second thickness,

a second semiconductor layer disposed on the second semiconductor oxide layer, and

a third semiconductor layer disposed on the second semiconductor layer; and

a gate structure disposed over the first material portion.

2. The device of claim 1, wherein the first thickness is greater than a sum of the second thickness and a thickness of the second semiconductor layer.

3. The device of claim 1, wherein the first semiconductor layer is free of dopant.

4. The device of claim 1, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer include different compositions.

5. The device of claim 1, further comprising a dielectric liner layer disposed along sidewalls of a portion of the fin structure, such that the dielectric liner layer physically contacts the first semiconductor oxide layer, the second semiconductor oxide layer, and the second semiconductor layer.

6. The device of claim 5, further comprising an isolation material disposed over the dielectric liner layer, wherein the isolation material and the dielectric liner layer form an isolation feature.

7. The device of claim 5, wherein the dielectric liner layer includes silicon nitride, silicon oxynitride, aluminum oxide, or a combination thereof.

8. The device of claim 5, wherein a thickness of the dielectric liner layer is about 20 angstroms to about 60 angstroms.

9. The device of claim 1, wherein the gate structure includes a gate electrode disposed over a gate dielectric, wherein the gate dielectric is disposed on the first semiconductor layer of the first material portion of the fin structure.

10. A device comprising:

a fin that includes;

a first layer that includes a first semiconductor material,

a second layer disposed on the first layer, wherein the second layer includes;

first portions having a semiconductor portion disposed over a semiconductor oxide portion, wherein the semiconductor portion includes a second semiconductor material; and

a second portion disposed between the first portions, wherein the second portion has the semiconductor oxide portion and is free of the semiconductor portion,

a third layer that includes a third semiconductor material disposed on the semiconductor portion of the first portions of the second layer, wherein a source region and a drain region are defined in the third layer, and

a fourth layer that includes a fourth semiconductor material disposed on the semiconductor oxide portion of the second portion of the second layer, wherein a channel region is defined in the fourth layer between the source region and the drain region defined in the third layer; and

a gate structure disposed over the channel region defined in the fourth layer of the fin, wherein the gate structure includes a gate stack having spacers disposed along sidewalls of the gate stack.

11. The device of claim 10, wherein a thickness of the first portions of the second layer is less than a thickness of the second portion of the second layer.

12. The device of claim 10, wherein:

the first semiconductor material of the first layer includes silicon;

the second semiconductor material of the semiconductor portion of the first portions of the second layer and the semiconductor oxide portion of the first portions and the second portion of the second layer include silicon and germanium, wherein the semiconductor oxide portion of the first portions and the second portion of the second layer further include oxygen;

the third semiconductor material of the third layer includes silicon and dopant; and

the fourth semiconductor material of the fourth layer includes silicon and is substantially free of dopant.

13. The device of claim 12, wherein the third semiconductor material of the third layer further includes germanium.

14. The device of claim 10, wherein a thickness of the semiconductor oxide portion of the first portions of the second layer is less than a thickness of the semiconductor oxide portion of the second portion of the second layer.

15. The device of claim 10, wherein the second semiconductor material of the semiconductor portion of the first portions of the second layer includes a compound semiconductor material and the fourth semiconductor material of the fourth layer includes an elementary semiconductor material.

16. A device comprising:

a fin structure disposed on a substrate, wherein the fin structure includes;

a first silicon layer,

a silicon germanium oxide layer disposed on the first silicon layer, wherein the silicon germanium oxide layer has a first portion having a first thickness, a second portion having a second thickness, and a third portion having the second thickness, wherein the first portion is disposed between the second portion and the third portion, and further wherein the first thickness is greater than the second thickness,

a silicon germanium layer disposed on the second portion of the silicon germanium oxide layer and the third portion of the silicon germanium oxide layer,

a semiconductor layer disposed on the silicon germanium layer, and

a second silicon layer disposed on the first portion of the silicon germanium oxide layer; and

a high-k/metal gate disposed on the second silicon layer.

17. The device of claim 16, wherein the second silicon layer is undoped.

18. The device of claim 16, wherein a thickness of the second silicon layer is about 10 nm to about 40 nm.

19. The device of claim 16, wherein the semiconductor layer is a third silicon layer.

20. The device of claim 16, wherein the silicon germanium layer is a first semiconductor germanium layer and the semiconductor layer is a second semiconductor germanium layer.