Resistive memory device having a template layer
First Claim
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1. A memory device, comprising:
- a template layer; and
a memory layer connected to the template layer, wherein the memory layer has a variable resistance, and wherein a crystalline structure of the memory layer matches a crystalline structure of the template layer.
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Abstract
A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.
20 Citations
24 Claims
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1. A memory device, comprising:
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a template layer; and a memory layer connected to the template layer, wherein the memory layer has a variable resistance, and wherein a crystalline structure of the memory layer matches a crystalline structure of the template layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of manufacturing a memory device, the method comprising:
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forming a template layer; and connecting a memory layer to the template layer, wherein the memory layer has a variable resistance, and wherein a crystalline structure of the memory layer matches a crystalline structure of the template layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of using a memory device, the memory device comprising a template layer and a memory layer connected to the template layer, wherein the memory layer has a variable resistance, and wherein a crystalline structure of the memory layer matches a crystalline structure of the template layer, the method comprising:
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applying a first voltage difference across the template layer and the memory layer, whereby an electric field is generated in the memory layer, and such that a resistivity state of the memory layer is changed; applying a second voltage difference across the template layer and the memory layer; while the second voltage difference is applied, causing a first current to be conducted through the template layer and the memory layer; and determining the resistivity state of the memory layer based on the second voltage difference and the first current. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification