Isolated DC-DC converter

• US 10,622,908 B2
• Filed: 12/29/2017
• Issued: 04/14/2020
• Est. Priority Date: 09/19/2017
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Granato, Maurizio, Frattini, Giavanni, Baranwal, Shailendra Kumar
• Primary Examiner(s): Gblende, Jeffrey A
• Assistant Examiner(s): Rivera-Perez, Carlos O
• Application Number:
  US15/859,145
• Publication Number:
  US 20190089263A1
• Time in Patent Office: 837 Days
• Field of Search: 363 15- 2103, 363 37, 363 40- 48, 363 62, 363 65, 363 67- 72, 363 74, 363 95- 99, 363123-127, 363131-134, 323205-211, 323222-226, 323235-238, 323266, 323271-275, 323282-287, 323351
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 1/0058 by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33573 Full-bridge at primary side of an isolation transformer
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

In described examples, an isolated DC-DC converter includes an input node for receiving an input voltage, and a transformer including a primary side having first and second terminals and a ground. First and second high-side switches are coupled between the input node and the first and second terminals, respectively. A first low-side switch is coupled between the first terminal and the ground, and through a first voltage limiter to be activated by a voltage at the second terminal. A second low-side switch is coupled between the second terminal and the ground, and through a second voltage limiter to be activated by a voltage at the first terminal. A switch controller controls the high-side switches so that voltages across the high-side switches are alternatingly zero, using a current through the primary side to alternatingly charge one terminal to an input voltage and discharge the other terminal to a ground voltage.

Claims

1. An isolated DC-DC converter, comprising:

an input node configured to have an input voltage;

a transformer including a primary side having first and second terminals and a primary ground terminal;

first and second high-side switches, the first high-side switch coupled between the first terminal and the input node, and the second high-side switch coupled between the second terminal and the input node;

first and second voltage limiters;

a first low-side switch coupled between the first terminal and the primary ground terminal, the first low-side switch having a gate coupled through the first voltage limiter to the second terminal;

a second low-side switch coupled between the second terminal and the primary ground terminal, the second low-side switch having a gate coupled through the second voltage limiter to the first terminal; and

a switch controller configured to;

close the first high-side switch to cause a first voltage across the first high side switch to be zero;

during a first phase, open the first high-side switch, while keeping the second high-side switch open, to enable a current through the primary side to reduce a second voltage across the second high-side switch to zero by charging the second terminal to the input voltage and discharging the first terminal;

close the second high-side switch when the second voltage is zero; and

during a second phase, open the second high-side switch, while keeping the first high-side switch open, to enable the current through the primary side to reduce the first voltage to zero by charging the first terminal to the input voltage and discharging the second terminal.

2. The converter of claim 1, further comprising:

a first bootstrap circuit coupled between the second terminal and a gate of the first high-side switch; and

a second bootstrap circuit coupled between the first terminal and a gate of the second high-side switch;

the first and second bootstrap circuits configured to be charged by the current through the primary side to a voltage higher than the input voltage.

3. The converter of claim 1, wherein the first and second low-side switches are self-driving.

4. The converter of claim 1, wherein:

the first voltage limiter includes a first transistor having a drain coupled to the second terminal, a source, and a gate;

the second voltage limiter includes a second transistor having a drain coupled to the first terminal, a source, and a gate;

the gate of the first low-side switch is coupled to the source of the first transistor;

the gate of the second low-side switch is coupled to the source of the second transistor; and

the gate of the first transistor and the gate of the second transistor are coupled to a voltage node, the voltage node configured to receive a fixed voltage less than or equal to a bias voltage of gates of the first and second low-side switches.

5. The converter of claim 1, wherein the switch controller is coupled through a first level shifter to a gate of the first high-side switch, the switch controller is coupled through a second level shifter to a gate of the second high-side switch, the switch controller is configured to generate respective control voltages to the first and second level shifters, and the first and second high-side switches are configured to close responsive to the respective control voltages.

6. The converter of claim 1, wherein a bias voltage of gates of the first and second low-side switches is less than the input voltage.

7. The converter of claim 1, wherein the first and second high-side switches include laterally diffused metal oxide semiconductor (LDMOS) transistors.

8. The converter of claim 1, further comprising:

an output node configured to have an output voltage;

the transformer including a secondary side having first and second secondary terminals and a secondary ground terminal;

first and second secondary high-side switches, the first secondary high-side switch coupled between the first secondary terminal and the output node, and the second secondary high-side switch coupled between the second secondary terminal and the output node;

a third voltage limiter that includes a third transistor having a drain coupled to the second secondary terminal, a source, and a gate;

a fourth voltage limiter that includes a fourth transistor having a drain coupled to the first secondary terminal, a source, and a gate;

a first secondary low-side switch coupled between the first secondary terminal and the secondary ground terminal, the first secondary low-side switch having a gate coupled to the source of the third transistor;

a second secondary low-side switch coupled between the second secondary terminal and the secondary ground terminal, the second secondary low-side switch having a gate coupled to the source of the fourth transistor; and

a secondary switch controller configured to alternatingly;

close a selected one of the first and second secondary high-side switches at times corresponding to a frequency of the converter to cause a voltage across the selected secondary high-side switch to be zero; and

open the selected secondary high-side switch when a current through the secondary side is zero and a voltage across the selected secondary high-side switch is zero.

9. The converter of claim 8, wherein the input voltage is more than 10 volts above a voltage at the primary ground terminal, and the output voltage is more than 10 volts above a voltage at the secondary ground terminal.

10. A method of driving an isolated DC-DC converter, the method comprising:

responsive to a voltage at a first terminal of a primary side of a transformer reaching an input voltage of an input node, causing a first high-side switch to connect the first terminal to the input node, and such that, while the first high-side switch connects the first terminal to the input node, the voltage at the first terminal, which is coupled to a gate of a first low-side switch, causes the first low-side switch to connect a second terminal of the primary side of the transformer to a primary ground terminal;

causing the first high-side switch to disconnect the first terminal from the input node, while keeping the second terminal disconnected from the input node, to enable a current through the primary side to charge the second terminal to the input voltage, while discharging the first terminal;

responsive to a voltage at the second terminal reaching the input voltage, causing a second high-side switch to connect the second terminal to the input node, such that while the second high-side switch connects the second terminal to the input node, the voltage at the second terminal, which is coupled to a gate of a second low-side switch, causes the second low-side switch to connect the first terminal to the primary ground terminal; and

causing the second high-side switch to disconnect the second terminal from the input node, while keeping the first terminal disconnected from the input node, to enable the current through the primary side to charge the first terminal to the input voltage, while discharging the second terminal.

11. The method of claim 10, further comprising:

connecting a first secondary terminal of a secondary side of the transformer to an output node having an output voltage at first times corresponding to a frequency of the converter;

connecting a second secondary terminal of the secondary side of the transformer to a secondary ground terminal when the voltage at the first secondary terminal equals the output voltage;

disconnecting the first secondary terminal from the output node responsive to;

a current through the secondary side being zero; and

a voltage between the first secondary terminal and the output node being zero;

disconnecting the second secondary terminal from the secondary ground terminal when the voltage at the first secondary terminal equals a voltage of the secondary ground terminal;

connecting the second secondary terminal to the output node at second times corresponding to the frequency of the converter;

connecting the first secondary terminal to the secondary ground terminal when the voltage at the second secondary terminal equals the output voltage;

disconnecting the second secondary terminal from the output node responsive to;

the current through the secondary side being zero; and

a voltage between the second secondary terminal and the output node being zero; and

disconnecting the first secondary terminal from the secondary ground terminal when the voltage at the second secondary terminal equals the voltage of the secondary ground terminal.

12. The method of claim 10, further comprising:

disconnecting the second terminal from the primary ground terminal when the voltage at the first terminal equals a voltage of the primary ground terminal; and

disconnecting the first terminal from the primary ground terminal when the voltage at the second terminal equals the voltage of the primary ground terminal.

13. An isolated DC-DC converter, comprising:

an input node configured to have an input voltage;

an output node configured to have an output voltage;

a transformer including;

a primary side having first and second primary terminals and a primary ground terminal, and a secondary side having first and second secondary terminals and a secondary ground terminal;

first and second primary high-side transistors, the first primary high-side transistor coupled between the first primary terminal and the input node, and the second primary high-side transistor coupled between the second primary terminal and the input node;

first and second primary voltage limiters;

a first primary low-side transistor coupled between the first primary terminal and the primary ground terminal, the first primary low-side transistor having a gate coupled through the first primary voltage limiter to the second primary terminal;

a second primary low-side transistor coupled between the second primary terminal and the primary ground terminal, the second primary low-side transistor having a gate coupled through the second primary voltage limiter to the first primary terminal;

first and second secondary high-side transistors, the first secondary high-side transistor coupled between the first secondary terminal and the output node, and the second secondary high-side transistor coupled between the second secondary terminal and the output node;

first and second secondary voltage limiters;

a first secondary low-side transistor coupled between the first secondary terminal and the secondary ground terminal, the first secondary low-side transistor having a gate coupled through the first secondary voltage limiter to the second secondary terminal;

a second secondary low-side transistor coupled between the second secondary terminal and the secondary ground terminal, the second secondary low-side transistor having a gate coupled through the second secondary voltage limiter to the first secondary terminal; and

at least one switch controller configured to;

close the first primary high-side transistor to cause a first voltage across the first primary high-side transistor to be zero;

during a first phase, open the first primary high-side transistor, while keeping the second primary high-side transistor open, to enable a current through the primary side to reduce a second voltage across the second primary high-side transistor to zero by charging the second primary terminal to the input voltage and discharging the first primary terminal;

close the second primary high-side transistor when the second voltage is zero; and

during a second phase, open the second primary high-side transistor, while keeping the first primary high-side transistor open, to enable the current through the primary side to reduce the first voltage to zero by charging the first primary terminal to the input voltage and discharging the second primary terminal.

14. The converter of claim 13, wherein the at least one switch controller is configured to alternatingly:

close a selected one of the first and second secondary high-side transistors at times corresponding to a frequency of the converter to cause a voltage across the selected secondary high-side transistor to be zero; and

open the selected secondary high-side transistor when a current through the secondary side is zero and a voltage across the selected secondary high-side transistor is zero.

15. The converter of claim 13, wherein the primary and secondary high-side transistors include laterally diffused metal oxide semiconductor (LDMOS) transistors.

16. The converter of claim 13, wherein:

the first primary voltage limiter includes a first transistor having a drain coupled to the second primary terminal, a source, and a gate;

the second primary voltage limiter includes a second transistor having a drain coupled to the first primary terminal, a source, and a gate;

the gate of the first primary low-side switch is coupled to the source of the first transistor;

the gate of the second primary low-side switch is coupled to the source of the second transistor;

the gate of the first transistor and the gate of the second transistor are coupled to a primary voltage node, the primary voltage node configured to receive a fixed voltage less than or equal to a bias voltage of gates of the first and second primary low-side transistors; and

the first secondary voltage limiter includes a third transistor having a drain coupled to the second secondary terminal, a source, and a gate;

the second secondary voltage limiter includes a fourth transistor having a drain coupled to the first secondary terminal, a source, and a gate;

the gate of the first secondary low-side switch is coupled to the source of the third transistor;

the gate of the second secondary low-side switch is coupled to the source of the fourth transistor; and

the gate of the third transistor and the gate of the fourth transistor are coupled to a secondary voltage node, the secondary voltage node configured to receive a fixed voltage less than or equal to a bias voltage of gates of the first and second secondary low-side transistors.

17. The converter of claim 13, further comprising:

a first bootstrap circuit coupled between the second primary terminal and a gate of the first primary high-side transistor; and

a second bootstrap circuit coupled between the first primary terminal and a gate of the second primary high-side transistor;

the first and second bootstrap circuits configured to be charged by the current through the primary side to a voltage higher than the input voltage.

18. The converter of claim 13, wherein the first and second primary low-side transistors and the first and second secondary low-side transistors are self-driving.