Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

• US 10,622,990 B2
• Filed: 08/03/2018
• Issued: 04/14/2020
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Brindle, Christopher N., Stuber, Michael A., Kelly, Dylan J., Kemerling, Clint L., Imthurn, George, Burgener, Mark L., Welstand, Robert B.
• Primary Examiner(s): Nguyen, Niki H
• Application Number:
  US16/054,959
• Publication Number:
  US 20190089348A1
• Time in Patent Office: 620 Days
• Field of Search: 257347, 257352, 257E29242, 257105, 257 40, 257348, 257402, 257403, 257E29255, 257E29281, 257E27112, 257E29151, 257E29287, 257E2928, 257E29286, 257E29297, 257E29296, 327546, 455333, 455425, 4555501
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claims

1. An RF switch circuit for switching RF signals, comprising:

(A) a first RF port;

(B) a second RF port; and

(C) a pass transistor grouping having a first node coupled to the first RF port and a second node coupled to the second RF port, the pass transistor grouping comprising a first two or more accumulated charge control N-type MOSFETs (ACC N-MOSFETs) arranged in a stacked configuration; and

wherein;

(a) each ACC N-MOSFET of the first two or more ACC N-MOSFETs comprises;

(i) a first gate, a first drain, a first source, a first gate oxide layer, and a first body, wherein the first gate oxide layer is positioned between the first gate and the first body; and

(ii) a first accumulated charge sink (ACS) region connected to the first body;

(b) the pass transistor grouping configured to couple the first RF port with the second RF port in a pass transistor grouping first state;

(c) the pass transistor grouping configured to isolate the first RF port from the second RF port in a pass transistor grouping second state, and wherein the pass transistor grouping is configured to have a first bias voltage applied to the first ACS region to remove or otherwise control, via the first ACS region, charge that, without the first bias voltage applied, would accumulate in the first body in the pass transistor grouping second state; and

(d) the first bias voltage being substantially negative with respect to ground, the first drain and the first source.

2. The RF switch circuit of claim 1, further comprising a shunt transistor grouping having a first node coupled to the first RF port and a second node coupled to ground, and the shunt transistor grouping comprising a second two or more ACC N-MOSFETs arranged in a stacked configuration,

wherein:

(a'"'"') each ACC N-MOSFET of the second two or more ACC N-MOSFETs comprises;

(i'"'"') a second gate, a second drain, a second source, a second body and a second gate oxide layer, wherein the second gate oxide layer is positioned between the second gate and the second body; and

(ii'"'"') a second accumulated charge sink (ACS) region is connected to the second body;

(b'"'"') the shunt transistor grouping configured to shunt the first RF port with the first RF port being coupled to ground in a shunt transistor grouping first state;

(c'"'"') the shunt transistor grouping configured to isolate the first RF port from ground in a shunt transistor grouping second state, and wherein the shunt transistor grouping is configured to have a second bias voltage applied to the second ACS region to remove or otherwise control, via the second ACS region, charge that, without the second bias voltage applied, would accumulate in the second body in the shunt transistor grouping second state; and

(d'"'"') the second bias voltage being substantially negative with respect to ground, the second drain and the second source.

3. The RF switch circuit of claim 2, wherein:

the pass transistor grouping is controllable by a first switch control signal; and

the shunt transistor grouping is controllable by a second switch control signal.

4. The RF switch circuit of claim 3, wherein:

the pass transistor grouping is enabled in the pass transistor grouping first state, by the first switch control signal, to couple the first RF port with the second RF port and the shunt transistor grouping is disabled in the shunt transistor grouping second state, by the second switch control signal, to isolate the first RF port from ground; and

the shunt transistor grouping is enabled in the shunt transistor grouping first state, by the second switch control signal, to shunt the first RF port to ground with the first RF port being coupled to ground and the pass transistor grouping is disabled in the pass transistor grouping second state, by the first switch control signal, to isolate the first RF port from the second RF port.

5. The RF switch circuit of claim 4, wherein the first two or more ACC N-MOSFETs arranged in the stacked configuration include respective gate resistors coupled to respective gates of the first two or more ACC N-MOSFETs, and wherein the second two or more ACC N-MOSFETs arranged in the stacked configuration include respective gate resistors coupled to respective gates of the second two or more ACC N-MOSFETs.

6. The RF switch circuit of claim 4, wherein the RF circuit is incorporated in a cellular communication device.

7. The RF switch circuit of claim 6, wherein the cellular communication device includes a GSM mode of operation.

8. The RF switch circuit of claim 6, wherein the cellular communication device is capable of transmitting in a cellular communication system at a level below −

30 dBm for one or more harmonics of a fundamental frequency.

9. The RF switch circuit of claim 2, wherein the first two or more ACC N-MOSFETs and the second two or more ACC N-MOSFETs respectively include a thin-film semiconductor layer in a silicon on insulator (SOI) substrate.

10. The RF switch circuit of claim 2, wherein the RF switch circuit is included on a single die.

21. The RF switch of claim 5, wherein the respective gate resistors have a value of at least 30 k ohms.

23. The RF switch of claim 1, wherein the first bias voltage being substantially negative with respect to ground, the first drain and the first source comprises the first bias voltage being more than one volt negative with respect to ground, the first drain and the first source.

24. The RF switch of claim 2, wherein the second bias voltage being substantially negative with respect to ground, the second drain and the second source comprises the second bias voltage being more than one volt negative with respect to ground, the second drain and the second source.

25. The RF switch circuit of claim 2, comprising a single-pole, multiple-throw RF switch that comprises two or more of the RF switch circuits of claim 2.

11. A single-pole, multiple-throw RF switch comprising:

a plurality of pass transistor groupings i, i=1, 2, . . . N, with i being two or greater;

a plurality of corresponding first RF ports i, i=1, 2, . . . N, with i being two or greater;

a second RF port;

wherein;

two or more pass transistor groupings of the plurality of pass transistor groupings to respectively couple two or more corresponding first RF ports with the second RF port;

the plurality of pass transistor groupings respectively comprises first two or more ACC N-MOSFETs arranged in a stacked configuration;

each ACC N-MOSFET of respective first two or more ACC N-MOSFETs comprises a first body, a first gate, a first drain, a first source and a first gate oxide layer, wherein the first gate oxide layer is positioned between the first gate and the first body, and a first accumulated charge sink (ACS) region connected to the first body;

one of the two or more pass transistor groupings, i, configured to couple one corresponding first RF port, i, with the second RF port in a pass transistor grouping first state;

other of the two or more pass transistor groupings, other than the one of the two or more pass transistor groupings, i, configured to isolate the two or more corresponding first RF ports, other than the one corresponding first RF port, i, from the second RF port in a pass transistor grouping second state, and wherein the other pass transistor groupings of the two or more pass transistor groupings, other than the one of the two or more pass transistor groupings, i, are configured to have a first bias voltage applied to the first ACS region to remove or otherwise control, via the first ACS region, charge that, without the first bias voltage applied, would accumulate in the first body in the pass transistor grouping second state;

the first bias voltage being substantially negative with respect to ground, the first drain and the first source.

12. The single-pole, multiple-throw RF switch of claim 11, wherein:

(a) for the one of the two or more pass transistor groupings, i, in the pass transistor grouping first state; and

(b) for the other pass transistor groupings, other than the one of the two or more pass transistor groupings, i, in the pass transistor grouping second state;

the single-pole, multiple-throw RF switch to;

(i) for the one of the two or more pass transistor groupings, i, couple the one corresponding first RF port, i, with the second RF port; and

(ii) for the other pass transistor groupings of the two or more pass transistor groupings, other than the one of the two or more pass transistor groupings, i, isolate the two or more corresponding first RF ports, other than the one corresponding first RF port, i, from the second RF port.

13. The single-pole, multiple-throw RF switch of claim 12, wherein the ACC N-MOSFETs include respective gate resistors coupled to respective gates thereof.

14. The single-pole, multiple-throw RF switch of claim 12, wherein the RF switch is incorporated in a cellular communication device.

15. The single-pole, multiple-throw RF switch of claim 14, wherein the cellular communication device includes a GSM mode of operation.

16. The single-pole, multiple-throw RF switch of claim 14, wherein the cellular communication device is capable of transmitting in a cellular communication system at a level below −

30 dBm for one or more harmonics of a fundamental frequency.

17. The single-pole, multiple-throw RF switch of claim 12, wherein the ACC N-MOSFETs respectively include a thin-film semiconductor layer in a silicon on insulator (SOI) substrate.

18. The single-pole, multiple-throw RF switch of claim 12, wherein the single-pole, multiple-throw RF switch is included on a single die.

19. The single-pole, multiple-throw RF switch of claim 12, and further comprising:

a plurality of shunt transistor groupings i, i=1, 2, . . . N, i being two or greater, respectively corresponding to the plurality of pass transistor groupings i, i=1, 2, . . ., N, i being two or greater;

two or more shunt transistor groupings of the plurality of shunt transistor groupings to respectively couple two or more corresponding first RF ports and ground in a shunt transistor grouping first state;

the plurality of shunt transistor groupings respectively comprises second two or more ACC N-MOSFETs arranged in a stacked configuration;

each ACC-N-MOSFET of the second two or more ACC N-MOSFETs comprises a second body, a second gate, a second drain, a second source and a second gate oxide layer, wherein the second gate oxide layer is positioned between the second gate and the second body, and a second accumulated charge sink (ACS) region connected to the second body;

one of the two or more shunt transistor groupings, i, configured to shunt one corresponding first RF port, i, with the one corresponding first RF port, i, being coupled to ground in the shunt transistor grouping first state;

other of the two or more shunt transistor groupings, other than the one of the two or more shunt transistor groupings, i, configured to isolate the two or more corresponding first RF ports, other than the one corresponding first RF port, i, from ground in a shunt transistor grouping second state, and wherein the other shunt transistor groupings of the two or more shunt transistor groupings, other than the one of the two or more shunt transistor groupings, i, are configured to have a second bias voltage applied to the second ACS region to remove or otherwise control, via the second ACS region, charge that, without the second bias voltage applied, would accumulate in the second body in the shunt transistor grouping second state;

the second bias voltage being substantially negative with respect to the ground, the second drain and the second source.

20. The single-pole, multiple-throw RF switch of claim 19, wherein:

(a) for the one of the two or more shunt transistor groupings, i, in the shunt transistor grouping first state; and

(b) for the other shunt transistor groupings of the two or more shunt transistor groupings, other than the one of the two or more shunt transistor groupings, i, in the second shunt transistor grouping state;

the RF single-pole, multiple- throw switch to;

(i) for the one of the two or more shunt transistor groupings, i, shunt the one corresponding first RF port, i, with the one corresponding first RF port, i, being coupled to ground; and

(ii) for the other shunt transistor groupings of the two or more shunt transistor groupings, other than the one of the two or more shunt transistor groupings, i, isolate the two or more corresponding first RF ports, other than the one corresponding first RF port, i, from ground.

22. The RF switch of claim 13, wherein the respective gate resistors have a value of at least 30 k ohms.