Tuning capacitance to enhance FET stack voltage withstand

• US 10,622,992 B2
• Filed: 12/01/2017
• Issued: 04/14/2020
• Est. Priority Date: 04/26/2007
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Englekirk, Robert Mark
• Primary Examiner(s): Patel, Reema
• Application Number:
  US15/829,773
• Publication Number:
  US 20180159530A1
• Time in Patent Office: 865 Days
• Field of Search: None
• CPC Class Codes: H01H 11/00 Apparatus or processes specially adapted for the manufacture of electric switches processes specially adapted for manufacture of rectilinearly movable switches having a plurality of operating members associated with different sets of contacts, e.g. keyboards, H01H13/88
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: Y10T 29/49105 Switch making

Abstract

An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Claims

1. A voltage distribution-balanced stack of series coupled transistors, comprising:

a stack of series coupled transistors comprising a first transistor having a first intrinsic drain source capacitance Cds and a second transistor having a second intrinsic Cds, wherein the second intrinsic drain-source capacitance Cds differs by at least a predetermined amount to the first intrinsic drain-source capacitance Cds.

2. The voltage distribution-balanced stack of claim 1, wherein the first transistor has a first transistor size and the second transistor has a second transistor size different from the first transistor size.

3. The voltage distribution-balanced stack of claim 2, wherein the first transistor size is smaller than the second transistor size.

4. The voltage distribution-balanced stack of claim 1, wherein the first intrinsic drain source capacitance Cds is lower than the second intrinsic drain-source capacitance Cds.

5. The voltage distribution-balanced stack of claim 1, further comprising:

a top endnode at a top of the stack of series coupled transistors;

a bottom endnode at a bottom of the stack of series coupled transistors;

a plurality of internal nodes between pairs of adjacent transistors of the stack of series coupled transistors; and

at least one compensation capacitor coupled across at least one of;

i) the top endnode and at least one node of the plurality of internal nodes, ii) at least two nodes of the plurality of internal nodes, iii) at least one node of the plurality of internal nodes and the bottom endnode, iv) the top endnode and the bottom endnode, or v) at least one of the plurality of internal nodes and ground, to voltage balance the stack of series coupled transistors.

6. The voltage distribution-balanced stack of claim 1, further comprising:

a top endnode at a top of the stack of series coupled transistors;

a plurality of internal nodes between pairs of adjacent transistors of the stack of series coupled transistors; and

one or more compensation capacitors coupled across intrinsic drain-source capacitances Cds of the transistors of the stack of series coupled transistors, to voltage balance the stack of series coupled transistors.

7. The voltage distribution-balanced stack of claim 5, wherein the at least one compensation capacitor is coupled to ground.

8. The voltage distribution-balanced stack of claim 5, wherein the first transistor has a first transistor size and the second transistor has a second transistor size different from the first transistor size.

9. The voltage distribution-balanced stack of claim 5, wherein the first transistor size is smaller than the second transistor size.

10. The voltage distribution-balanced stack of claim 5, wherein the first intrinsic drain-source capacitance Cds is lower than the second intrinsic drain-source capacitance Cds.

11. A stacked transistor RF switch apparatus, comprising:

a) a transistor stack including a plurality of constituent transistors all coupled in series connection drain to source to form a series string for which internal nodes are those between adjacent transistors, each constituent transistor having an intrinsic drain-source capacitance Cds; and

b) at least two constituent transistors configured so their intrinsic drain-source capacitance Cds values differ from each other by at least 2%.

12. A stacked transistor RF switch apparatus, comprising:

a transistor stack including a plurality of constituent transistors all coupled in series connect on drain to source to form a series string for which internal nodes are those between adjacent transistors, each constituent transistor having an intrinsic drain-source capacitance Cds; and

a first discrete capacitive element disposed in parallel to one of at least two constituent transistors drain-source and a second discrete capacitive element disposed in parallel to another of the least two constituent transistors drain-source, the at least two constituent transistors intrinsic drain-source capacitance Cds values differing from each other by at least 2%.