Logic drive using standard commodity programmable logic IC chips

• US 10,623,000 B2
• Filed: 02/13/2019
• Issued: 04/14/2020
• Est. Priority Date: 02/14/2018
• Status: Active Grant

• Current Assignee: Icometrue Company Ltd.
• Original Assignee: Icometrue Company Ltd.
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Le, Don P
• Application Number:
  US16/275,272
• Publication Number:
  US 20190253056A1
• Time in Patent Office: 426 Days
• Field of Search: 326 41
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1533 : the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H03K 19/17728 : Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 : Structural details of routing resources
• CPC Class Codes: H03K 19/1776 : for memories
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

Claims

1. A programmable interconnection system based on a multi-chip package comprising:

an interposer comprising a first programmable interconnect and a second programmable interconnect therein;

a first semiconductor chip over the interposer, wherein the first semiconductor chip comprises a configurable switch therein, and wherein the configurable switch couples to the first and second programmable interconnects, respectively, and is configured to control connection between the first and second programmable interconnects and to connect the first programmable interconnect to the second programmable interconnect; and

a second semiconductor chip over the interposer and on a same plane as the first semiconductor chip, wherein the second programmable interconnect couples to the second semiconductor chip, and the first programmable interconnect couples to the second semiconductor chip through the configurable switch and the second programmable interconnect.

2. The programmable interconnection system of claim 1, wherein the first programmable interconnect comprises a copper via of the interposer, wherein the copper via is through a silicon substrate of the interposer.

3. The programmable interconnection system of claim 1, wherein the first programmable interconnect is provided by multiple interconnection metal layers of the interposer, wherein each of the interconnection metal layers comprises a copper layer in a silicon-containing insulating dielectric layer of the interposer, wherein said each of the interconnection metal layers further comprises an adhesion layer at a sidewall and bottom of the copper layer.

4. The programmable interconnection system of claim 3, wherein the adhesion layer comprises titanium.

5. The programmable interconnection system of claim 3, wherein the silicon-containing insulating dielectric layer comprises silicon oxide.

6. The programmable interconnection system of claim 1 further comprising a third programmable interconnect over the interposer and the first and second semiconductor chips, wherein the third programmable interconnect is connected to the configurable switch through the first programmable interconnect.

7. The programmable interconnection system of claim 1, further comprising a metal interconnection scheme over the interposer and the first and second semiconductor chips and across an edge of the first semiconductor chip, wherein the metal interconnection scheme comprises an interconnection metal layers over the interposer and the first and second semiconductor chips and across an edge of the first semiconductor chip and a polymer layer on the interconnection metal layer, wherein the interconnection metal layer comprises a third programmable interconnect connected to the configurable switch through the first programmable interconnect, wherein the interconnection metal layers comprises a copper layer covered by the polymer layer, wherein the interconnection metal layers comprises an adhesion layer at a bottoms of the copper layer but not at a sidewall of the copper layer.

8. The programmable interconnection system of claim 6 further comprising a through via between the first and second semiconductor chips, on a same plane as the first and second semiconductor chips and over the interposer, wherein the third programmable interconnect is connected to the first programmable interconnect through the through via.

9. The programmable interconnection system of claim 1 further comprising first and second tin-containing bumps between the first semiconductor chip and the interposer, wherein the first tin-containing bump couples the configurable switch to the first programmable interconnect and the second tin-containing bump couples the configurable switch to the second programmable interconnect.

10. The programmable interconnection system of claim 1 further comprising a first and second copper bumps between the first semiconductor chip and the interposer, wherein the first copper bump couples the configurable switch to the first programmable interconnect and the second copper bump couples the configurable switch to the second programmable interconnect.

11. The programmable interconnection system of claim 1, wherein the first semiconductor chip comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

12. The programmable interconnection system of claim 1, wherein the first semiconductor chip comprises a dedicated programmable interconnection IC chip.

13. The programmable interconnection system of claim 1, wherein the second semiconductor chip comprises a dynamic-random-access-memory (DRAM) IC chip.

14. The programmable interconnection system of claim 1, wherein the second semiconductor chip comprises a graphic-processing-unit (GPU) chip.

15. The programmable interconnection system of claim 1, wherein the second semiconductor chip comprises a central-processing-unit (CPU) chip.

16. The programmable interconnection system of claim 1, wherein the interposer further comprises a third programmable interconnect therein, wherein the configurable switch further couples to the third programmable interconnect and is configured to control connection between the first and third programmable interconnects.

17. The programmable interconnection system of claim 1, wherein the first semiconductor chip comprises a memory cell therein, wherein the memory cell is configured to store a programming code to program the configurable switch.

18. The programmable interconnection system of claim 1, wherein the first semiconductor chip comprises an I/O circuit coupling to the second semiconductor chip through the second programmable interconnect, wherein the I/O circuit comprises a driver having a driving capability between 0.05 pF and 2 pF.

19. A programmable interconnection system based on a chip package comprising:

an interposer comprising a first programmable interconnect therein;

a semiconductor chip over the interposer, wherein the semiconductor chip comprises a configurable switch and a memory cell therein, wherein the memory cell is configured to store a programming code to program the configurable switch; and

a metal bump between the semiconductor chip and the interposer, wherein the configurable switch couples to the first programmable interconnect through the metal bump.

20. The programmable interconnection system of claim 19, wherein the first programmable interconnect comprises a copper via of the interposer, wherein the copper via is through a silicon substrate of the interposer.

21. The programmable interconnection system of claim 19, wherein the first programmable interconnect is provided by multiple interconnection metal layers of the interposer, wherein each of the interconnection metal layers comprises a copper layer in a silicon-containing insulating dielectric layer of the interposer, wherein said each of the interconnection metal layers further comprises an adhesion layer at a sidewall and bottom of the copper layer.

22. The programmable interconnection system of claim 19, wherein the semiconductor chip comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

23. The programmable interconnection system of claim 19, wherein the semiconductor chip comprises a dedicated programmable interconnection IC chip.

24. The programmable interconnection system of claim 19, wherein the interposer further comprises second, third and fourth programmable interconnects therein, wherein the configurable switch further couples to the second, third and fourth programmable interconnects and is configured to control connection from the first programmable interconnect to one or more of the second, third and fourth programmable interconnects.

25. The programmable interconnection system of claim 19, wherein the semiconductor chip comprises an I/O circuit coupling to the first programmable interconnect, wherein the I/O circuit comprises a driver having a driving capability between 0.05 pF and 2 pF.