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Combined hidden dynamic random-access devices utilizing selectable keys and key locators for communicating randomized data together with sub-channels and coded encryption keys

  • US 10,623,384 B2
  • Filed: 10/29/2018
  • Issued: 04/14/2020
  • Est. Priority Date: 06/12/2017
  • Status: Active Grant
First Claim
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1. One or more combined devices comprising:

  • a real or virtual master distributed auto-synchronous array (DASA) database or both one or more real and one or more virtual master distributed auto-synchronous array (DASA) databases located within or external to said one or more combined devices, where said (DASA) databases at least store and retrieve data and also include at least two or more partial distributed auto-synchronous array (DASA) databases wherein said partial DASA databases function in either an independent manner, a collaborative manner or both an independent manner and a collaborative manner, and wherein said master and partial DASA databases allow for bi-directional transmission of data to and from multiple partial user devices, to and from multiple partial access devices or to and from both partial user and partial access devices, wherein said one or more combined devices encrypt data transmitted to or decrypt data received from or both transmit said data to and decrypt said data received from said one or more combined devices that utilize one or more master keys, the one or more combined devices further comprising;

    at least one encrypter or decrypter or both an encrypter and a decrypter that encrypt or decrypt or both encrypt and decrypt said data or said associated data files or both said data and said associated data files that utilize one or more master keys and one or more key selectors, wherein said master keys and said key selectors produce a specific set of one or more executable encryption keys that encrypt or decrypt or both encrypt and decrypt said data or said associated data files or both said data and said associated data files where one or more said key selectors coincide with at least one value that directly corresponds with created cipher data or created cipher data files or both said created cipher data and said created cipher data files, and wherein said key selectors and said created cipher data and said created cipher data files produce result data and result data files where said created cipher data and said created cipher data files together with said result data and said result data files are sealed to produce encrypted data and encrypted data files that are only encrypted and decrypted with one or more said master keys and one or more said key selectors, wherein said master keys are executable coded cipher keys andwherein said data or said associated data files or both said data and said associated data files are a form of transmission(s) that are signals andwherein said one or more combined devices further comprises;

    a forward error correction encoder that encodes transmission(s) and provides a known degree of forward error correction to encoded transmission(s);

    a sub-channel encoder;

    a transmission(s) combiner that combines said encoded transmission(s) from said forward error correction encoder with transmission(s) from said sub-channel encoder;

    a transmission(s) encrypter that receives combined transmission(s) from said transmission(s) combiner, wherein said transmission(s) encrypter receives one or more encrypter keys (KE) and said combined transmission(s), where said combined transmission(s) are encrypted by said transmission(s) encrypter and sent to a transmission(s) transmitter and wherein said combined transmission(s) are in a form of cipher text;

    a transmission(s) receiver that receives said cypher text and sends said cypher text to a transmission(s) decrypter, where said cypher text is decrypted and wherein said encryption is for dynamically encrypted data on the move; and

    at least one computer processing unit (CPU) with computational capabilities that is connected to and controls a computer memory via an address bus and a data bus where said address bus accesses a designated range of computer memories and range of memory bits and said data bus provides a flow of transmission(s) into and out of said CPU and said computer memory.

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