Modulization of cache structure utilizing independent tag array and data array in microprocessor

• US 10,628,320 B2
• Filed: 06/03/2016
• Issued: 04/21/2020
• Est. Priority Date: 06/03/2016
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Tran, Thang
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Cheong, Andrew J
• Application Number:
  US15/172,906
• Publication Number:
  US 20170351610A1
• Time in Patent Office: 1,418 Days
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of L1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the cache is interfaced with one or more data index queues that comprise, upon occurrence of a conflict between at least one instruction requesting access to the data array and at least one other instruction that accessed the data array, at least one data index for accessing the data array associated with the at least one instruction. A tag array in the cache is interfaced with a tag queue that stores one or more tag entries associated with one or more data outputs read from the data array based on accessing the data array.

Claims

1. A microprocessor, comprising:

a data array in a cache of the microprocessor, the data array directly interfaced with one or more data index queues, wherein;

upon detection of a conflict between a plurality of instructions issued from an input queue requesting access to the data array, at least one data index associated with at least one of the instructions is stored into the one or more data index queues,

the at least one data index is kept in the one or more data index queues until after removal of the conflict, and

upon the removal of the conflict, the data array is accessed based on the at least one data index stored in the one or more data index queues;

a tag array in the cache accessed by the instructions prior to the detection of the conflict, the tag array interfaced with a tag queue that stores tag entries from the tag array, The tag entries associated with data outputs read from the data array in response to accessing the data array when executing the instruction, the tag entries being kept in the tag queue until after the removal of the conflict, the input queue directly communicating with the tag queue to prevent overflowing of the tag queue when the tag entries associated with the instructions are being kept in the tag queue; and

circuitry in the cache couple to the data array and the tag array, the circuitry configured, upon the removal of the conflict, to initiate resending the at least one of the instructions from the input queue without re-accessing the tag array and the one or more data index queues for storing the at least one data index.

2. The microprocessor of claim 1, wherein the circuitry comprises:

an interface circuit coupled with the data array and with at least one of the one or more data index queues to detect occurrence of the conflict; and

a circuit to store, based on the detection of the conflict, the at least one data index for accessing the data array in the at least one data index queue.

3. The microprocessor of claim 1, wherein the circuitry further comprises:

a circuit coupled to the tag array configured to detect at least one tag miss, wherein

the circuit is further configured to trigger removal of the at least one data index from the one or more data index queues based on information about the at least one tag miss.

4. The microprocessor of claim 1, further comprising:

a data queue interface with the data array for storing one or more data outputs from the data array.

5. The microprocessor of claim 4, wherein each tag entry of the one or more tag entries in the tag queue stored from the tag array is associated with one data output of the one or more data outputs stored in the data queue from the data array.

6. The microprocessor of claim 1, wherein:

the data array comprises a plurality of data banks, and

each data index queue of the one or more data index queues comprises an interface with a different data bank of the plurality of data banks.

7. The microprocessor of claim 1, further comprising:

a data translation look-aside buffer (DTLB) in the data cache associated with the tag array and accessed independently of the data array; and

a circuit coupled to the tag array and the DTLB configured to detect at least one tag miss.

8. The microprocessor of claim 1, further comprising:

a read pointer of a data index queue of the one or more data index queues indicating an entry in the data index queue for requesting access to the data array in relation to the at least one instruction;

a save read pointer of the data index queue for restoring a value of the read pointer after occurrence of the conflict when accessing the data array in relation to the at least one instruction; and

a write pointer of the data index queue indicating another entry in the data index queue for requesting access to the data array in relation to another instruction of the plurality of instructions.

9. The microprocessor of claim 1, wherein:

the at least one instruction is issued concurrently with at least one other instruction of the plurality of instructions, or

the at least one instruction is issued after the at least one other instruction.

10. A method executed by a microprocessor, comprising:

issuing, from an input queue, one or more instructions per clock cycle for accessing a data array in a cache of the microprocessor, the data array directly interfaced with one or more data index queues;

upon detection of a conflict between a plurality of instructions issued from the input queue requesting access to the data array, storing at least one data index associated with at least one of the instructions into the one or more data index queues;

keeping the at least one data index in the one or more data index queues until after removal of the conflict;

upon the removal of the conflict, accessing the data array based on the at least one data index stored in the one or more data index queues;

accessing, by the instructions prior to the detection of the conflict, a tag array in the cache interfaced with a ta queue;

storing, in the tag queue based on accessing the tag array, tag entries from the tag array, The tag entries associated with data outputs read from the data array in response to accessing the data array when executing the instructions;

keeping the tag entries in the tag queue until after the removal of the conflict communicating, by the input queue, directly with the tag queue to prevent overflowing of the tag queue when the tag entries associated with the instructions are being kept in the tag queue; and

upon the removal of the conflict, resending the at least one of the instructions from the input queue without re-accessing the tag array and the one or more data index queues for storing the at least one data index.

11. The method of claim 10, further comprising:

detecting at least one tag miss based on accessing the tag array; and

removing, from the one or more data index queues, the at least one data index based on information about the at least one tag miss.

12. The method of claim 10, further comprising:

directly accessing the data array, if at least one data index queue of the one or more data index queues is empty.

13. The method of claim 10, further comprising:

storing the one or more data outputs from the data array into a data queue interfaced with the data array.

14. The method of claim 13, wherein each tag entry of the one or more tag entries in the tag queue stored from the tag array is associated with one data output of one or more data outputs stored in the data queue from the data array.

15. The method of claim 10, further comprising:

incrementing a read pointer of a data index queue of the one or more data index queues based on the at least one instruction requesting access to the array, the read pointer indicating an entry in the data index queue for requesting access to the data array in relation to the at least one instruction;

incrementing, if no conflict occurs when accessing the data array in relation to the at least one instruction, a save read pointer of the data index queue;

restoring, if the conflict occurs when accessing the data array in relation to the at least one instruction, the read pointer based on a value of the save read pointer; and

incrementing, based on issuing an instruction of the plurality of instructions for accessing the data array, a write pointer of the data index queue indicating another entry in the data index queue for requesting access to the data array in relation to the instruction.

16. The method of claim 15, further comprising:

triggering indication that the data index is full when the write pointer is same as the save read pointer.

17. The method of claim 10, further comprising:

replaying the at least one instruction based on the at least one data index kept in the one or more data index queue when the conflict is removed.

18. The method of claim 10, wherein issuing the one or more instructions per clock cycle comprises:

issuing the at least one instruction concurrently with issuing at least one other instruction of the plurality of instructions.

19. The method of claim 10, wherein issuing the one or more instructions per clock cycle comprises:

issuing the at least one instruction after issuing at least one other instruction of the plurality of instructions.