Internal serial interface

• US 10,628,372 B2
• Filed: 02/08/2019
• Issued: 04/21/2020
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Ross, James Henry, Banowetz, Matthew Lee
• Primary Examiner(s): Tseng, Cheng Yuan
• Application Number:
  US16/271,441
• Publication Number:
  US 20190272251A1
• Time in Patent Office: 438 Days
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4286 using a handshaking protocol, e.g. RS232C link
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.

Claims

1. A communications interface for a radio frequency device, comprising:

a serial interface configured to receive data signals from a radio frequency front end component, the serial interface including a transmit block configured to provide data signals to at least one receive block; and

a clock generator configured to be activated to provide a first clock signal to the serial interface when first data received by the serial interface from the radio frequency front end component is to be transmitted via the serial interface to the receive block, the first clock signal being different than a second clock signal provided to the radio frequency front end component, the clock generator and the transmit block being configured to be disabled when the first data has been transmitted via the serial interface.

2. The communications interface of claim 1 wherein the at least one receive block includes a plurality of receive blocks configured to receive data signals, enable signals, and clock signals from the serial interface.

3. The communications interface of claim 2 wherein the plurality of receive blocks receive a common enable signal.

4. The communications interface of claim 2 wherein the plurality of receive blocks are individually enabled by the serial interface.

5. The communications interface of claim 1 further comprising a downstream device configured to receive the first data from the at least one receive block.

6. The communications interface of claim 5 wherein the downstream device includes an antenna switch module or a band switch.

7. The communications interface of claim 5 wherein the radio frequency front end component and the serial interface are formed on a first die, and the at least one receive block and downstream device are formed on a second die.

8. The communications interface of claim 5 wherein the downstream device includes a detector configured to determine when the receive block and downstream device are capable of receiving data and the downstream device communicates with the receive block to inhibit enablement of the receive block until the receive block and downstream device are capable of receiving data.

9. A wireless device, comprising:

a radio frequency front end component configured to receive input data signals and a first clock signal;

a serial interface configured to receive data signals from the radio frequency front end component and configured to provide data and enable signals to at least one receive block; and

a downstream device configured to receive the data from the at least one receive block and including a power on reset detector configured to determine when the at least one receive block and the downstream device are capable of receiving data, the power on reset detector controlling a switch that inhibits transmission of the enable signals until the at least one receive block and downstream device are capable of receiving data.

10. The device of claim 9 further comprising a clock generator configured to be enabled by the radio frequency front end component to provide a second clock signal to the serial interface when data is to be transmitted via the serial interface.

11. The device of claim 10 wherein the clock generator provides the second clock signal to the serial interface when enabled by the radio frequency front end.

12. The device of claim 11 wherein the clock generator is disabled when the data has been transmitted.

13. The device of claim 9 wherein the at least one receive block includes a plurality of receive blocks configured to receive data signals, enable signals, and clock signals from the serial interface.

14. The device of claim 13 wherein the plurality of receive blocks receive a common enable signal.

15. The device of claim 13 wherein the plurality of receive blocks are individually enabled by the serial interface.

16. The device of claim 9 wherein the downstream device further includes an antenna switch module or a band switch.

17. The device of claim 9 wherein the radio frequency front end and the serial interface are formed on a first die, and the at least one receive block and downstream device are formed on a second die.

18. The device of claim 9 wherein the switch includes at least one pull down resistor.

19. A wireless communications device comprising:

an antenna;

a radio frequency front end component coupled to the antenna; and

a communications interface including a serial interface configured to receive data signals from the radio frequency front end component, the serial interface including a transmit block configured to provide data signals to at least one receive block, the communications interface further including a clock generator configured to be activated to provide a first clock signal to the serial interface when first data received by the serial interface from the radio frequency front end component is to be transmitted via the serial interface to the receive block, the first clock signal being different than a second clock signal provided to the radio frequency front end component, the clock generator and the transmit block being configured to be disabled when the first data has been transmitted via the serial interface.