Dynamic management of programming states to improve endurance

• US 10,629,260 B2
• Filed: 09/28/2018
• Issued: 04/21/2020
• Est. Priority Date: 09/01/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Yang, Nian Niles, Manohar, Abhijeet
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US16/146,351
• Publication Number:
  US 20190035457A1
• Time in Patent Office: 571 Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/78 using programmable devices

Abstract

A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Claims

1. A method for reassigning programmed states in a multi-level cell (MLC) memory block of at least three bits per cell, the method comprising:

performing a first programming of original data to the MLC memory block using a program verify for single level cell (SLC) programming;

adjusting a read verify for a second programming wherein the adjusted read verify establish a number of states that correspond with a lower number of bits per cell than the at least three bits per cell; and

second programming new data using the adjusted read verify.

2. The method of claim 1 wherein a number of states corresponding with the second programming from the adjusted read verify is different from a number of states associated with the at least three bits per cell.

3. The method of claim 1 further comprising:

setting a programming flag to identify when the second programming uses the adjusted read verify.

4. The method of claim 3 further comprising:

receiving a read operation of the MLC memory block; and

utilizing the adjusted read verify after the second programming.

5. The method of claim 1 wherein the memory block is erased before the first programming and the second programming does not require erase.

6. The method of claim 1 wherein the at least three bits per cell comprises four bits per cell.

7. The method of claim 6 wherein the lower number of bits per cell comprises two bits per cell.

8. The method of claim 6 wherein the lower number of bits per cell comprises three bits per cell.

9. The method of claim 1 wherein the original data corresponds with an upper page and the new data corresponds with a lower page.

10. The method of claim 1 wherein the original data corresponds with a lower page and the new data corresponds with a upper page.

11. A storage device comprising:

a memory comprising memory blocks with circuitry for four bits per cell in the memory blocks;

a controller coupled with the memory that is configured to receive a programming request for the memory blocks; and

program state circuitry that first programs using single level cell (SLC) programming with a program verify level corresponding to SLC and that second programs using the SLC programming with a modified program verify level corresponding with two bits per cell.

12. The storage device of claim 11 wherein the second programming does not require erase.

13. The storage device of claim 11 wherein the controller sets a programming flag to identify when the modified program verify level is in use.

14. The storage device of claim 11 wherein the program state circuitry is part of the controller.

15. The storage device of claim 11 wherein the program state circuitry provides for four states after the second program, while the memory is designed for four bits per cell.

16. A storage device comprising:

a means for first programming of original data to a memory block using a program verify for single level cell (SLC) programming;

means for adjusting a read verify; and

means for second programming with the adjusted read verify, wherein the adjusted read verify establishes a number of states that correspond with a lower number of bits per cell than the first programming.

17. The storage device of claim 16 wherein the memory block comprises multi-level cell (MLC) memory.

18. The storage device of claim 16 further comprising:

means for setting a programming flag to identify when the second programming uses the adjusted read verify.

19. The method of claim 16 further comprising:

means for receiving a read operation for the original data for the memory block; and

means for utilizing the adjusted read verify after the second programming.

20. The method of claim 16 wherein the memory block is erased before the first programming and the second programming does not require erase.

21. The method of claim 16 wherein the original data corresponds with an upper page and the new data corresponds with a lower page.

22. The method of claim 16 wherein the original data corresponds with a lower page and the new data corresponds with an upper page.