Proactive reduction of re-read triggering

• US 10,629,273 B2
• Filed: 02/15/2019
• Issued: 04/21/2020
• Est. Priority Date: 02/15/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chen, Lei, Guo, Xin, Khakifirooz, Ali, Madraswala, Aliasgar, Wakchaure, Yogesh B.
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/276,695
• Publication Number:
  US 20190180829A1
• Time in Patent Office: 431 Days
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An embodiment of a semiconductor apparatus may include technology to determine an error rate associated with a read request for a persistent storage media, compare the determined error rate against a pre-fail threshold, and adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold. Other embodiments are disclosed and claimed.

Claims

1. A semiconductor apparatus for use with a persistent storage media, comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to;

determine an error rate associated with a read request for a persistent storage media,

compare the determined error rate against a pre-fail threshold, and

adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold.

2. The apparatus of claim 1, wherein the logic is further to:

determine the error rate based on a number of errors in a plane for a channel task;

cause an interrupt if the error rate exceeds the pre-fail threshold; and

calibrate a read reference shift in response to the interrupt.

3. The apparatus of claim 2, wherein the logic is further to:

calibrate the read reference shift based on an automatic read calibration of the persistent storage media.

4. The apparatus of claim 3, wherein the logic is further to:

adjust the read voltage shift direction based on a persistent storage media-provided voltage value.

5. The apparatus of claim 2, wherein the logic is further to:

calibrate the read reference shift based on a hard bit read of the persistent storage media with a level indicator.

6. The apparatus of claim 5, wherein the logic is further to:

adjust the read voltage shift direction based on a first number of symbols decoded to zero and a second number of symbols decoded to one.

7. The apparatus of claim 1, wherein the persistent storage media comprises NAND media.

8. The apparatus of claim 1, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

9. An electronic storage system, comprising:

persistent storage media; and

a controller communicatively coupled to the persistent storage media, the controller including logic to;

determine an error rate associated with a read request for the persistent storage media,

compare the determined error rate against a pre-fail threshold, and

adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold.

10. The system of claim 9, wherein the logic is further to:

determine the error rate based on a number of errors in a plane for a channel task;

cause an interrupt if the error rate exceeds the pre-fail threshold; and

calibrate a read reference shift in response to the interrupt.

11. The system of claim 10, wherein the logic is further to:

calibrate the read reference shift based on an automatic read calibration of the persistent storage media.

12. The system of claim 11, wherein the logic is further to:

adjust the read voltage shift direction based on a persistent storage media-provided voltage value.

13. The system of claim 10, wherein the logic is further to:

calibrate the read reference shift based on a hard bit read of the persistent storage media with a level indicator.

14. The system of claim 13, wherein the logic is further to:

adjust the read voltage shift direction based on a first number of symbols decoded to zero and a second number of symbols decoded to one.

15. A method of controlling storage, comprising:

determining an error rate associated with a read request for a persistent storage media;

comparing the determined error rate against a pre-fail threshold; and

adjusting a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold.

16. The method of claim 15, further comprising:

determining the error rate based on a number of errors in a plane for a channel task;

causing an interrupt if the error rate exceeds the pre-fail threshold; and

calibrating a read reference shift in response to the interrupt.

17. The method of claim 16, further comprising:

calibrating the read reference shift based on an automatic read calibration of the persistent storage media.

18. The method of claim 17, further comprising:

adjusting the read voltage shift direction based on a persistent storage media-provided voltage value.

19. The method of claim 16, further comprising:

calibrating the read reference shift based on a hard bit read of the persistent storage media with a level indicator.

20. The method of claim 19, further comprising:

adjusting the read voltage shift direction based on a first number of symbols decoded to zero and a second number of symbols decoded to one.